Browsing by Author "Yen, Chia-Chih"

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A Formal Method to Improve SystemVerilog Functional Coverage
(2012-01-01)
Cheng, An-Che
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Yen, Chia-Chih
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Jou, Jing-Yang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce deterministic test patterns for complete coverage. The framework is based on the functional coverage model (covergroup) provided by SystemVerilog, and it could be easily integrated to modern digital design flow. We synthesize a practical subset of covergroup language constructs to enable FTPG by a SAT-solver. An algorithm called MRRS is proposed to minimize the potential large complexity of the synthesized circuits. Preliminary experimental results demonstrate that MRRS could facilitate FTPG to achieve 43X speed-up in average while the maximum speed-up can reach 67X. To the best of our knowledge, this is the first paper which proposes an FTPG method that utilizes covergroups.
Accelerating Dynamic Peak Power Analysis Using An Essential-Signal-Based Methodology
(2011)
Shih, Che-Hua
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Yen, Chia-Chih
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Lin, Shen-Tien
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Lin, Hermes
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Jou, Jing-Yang
Accurate peak power measurement requires detailed switching and delay information for each signal over the entire simulation. Performing a full signal dump and power calculation for a long simulation run usually spends a large amount of time and disk space. In this paper, we propose an Essential-signal-based methodology which only performs power analysis over a small subset of the original simulation but still acquires the true peak power value. Experimental results show that the proposed methodology significantly decreases both time (about 18 X speedup) and disk space usage (about 87% reduction) against the traditional power analysis flow.
An optimum algorithm for compacting error traces for efficient design error debugging
(2006-11-01)
Yen, Chia-Chih
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Jou, Jing-Yang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Diagnosing counterexamples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate the designers' burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of the binary search algorithm to halve the search space recursively. Furthermore, it applies a novel theorem to guarantee gaining the shortest lengths for the error traces. Based on the optimum algorithm, we develop two robust heuristics to handle real designs. Experimental results demonstrate that our approaches greatly surpass previous work and, indeed, have promising solutions.
FSM-Based Formal Compliance Verification of Interface Protocols
(2010-09-01)
Shih, Che-Hua
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Yang, Ya-Ching
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Yen, Chia-Chih
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Huang, Juinn-Dar
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Jou, Jing-Yang
Verifying whether a building block conforms to a specific interface protocol is one of the important steps in a platform-based system-on-a-chip design methodology. There are limitations for most of the existing methods for interface protocol compliance verification. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel approach for interface protocol compliance verification. The properties of the interface protocol are first specified as a specification FSM. Then the compliance of interface logic is formally verified at the higher FSM level so that the required memory and runtime can be greatly reduced. Finally, it is shown theoretically and experimentally that the proposed algorithm possesses acceptably low time complexity for practical applications.