Browsing by Author "Yen, Ta-Kan"

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A Distributed Thread Scheduler for Dynamic Multithreading on Throughput Processors
(2013)
Yen, Ta-Kan
;
Kuo, Hsien-Kai
;
Lai, Bo-Cheng Charles
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
GPGPUs have emerged as one of the most widely used throughput processors. Deep multithreading and cache hierarchy are the two effective implementations to achieve high throughput computing in modern GPGPUs. However, these are two conflicting design options. Finding a proper design point between the two has become a significant performance factor to GPGPUs. This paper proposes a distributed thread scheduler for dynamic multithreading on GPGPUs. By demonstrating the trade-off issue between the multithreading and cache contention, the proposed scheduler dynamically adjusts the multithreading degree to achieve superior performance. With the proposed scheduler, the cache misses can be decreased by 20.6% and 37.9% on the L1 and L2 cache respectively. The overall performance can be enhanced by an average of 16.4%.
A Distributed Thread Scheduler for Dynamic Multithreading on Throughput Processors
(2013-01-01)
Yen, Ta-Kan
;
Kuo, Hsien-Kai
;
Lai, Bo-Cheng Charles
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
GPGPUs have emerged as one of the most widely used throughput processors. Deep multithreading and cache hierarchy are the two effective implementations to achieve high throughput computing in modern GPGPUs. However, these are two conflicting design options. Finding a proper design point between the two has become a significant performance factor to GPGPUs. This paper proposes a distributed thread scheduler for dynamic multithreading on GPGPUs. By demonstrating the trade-off issue between the multithreading and cache contention, the proposed scheduler dynamically adjusts the multithreading degree to achieve superior performance. With the proposed scheduler, the cache misses can be decreased by 20.6% and 37.9% on the L1 and L2 cache respectively. The overall performance can be enhanced by an average of 16.4%.
A Locality-Aware Dynamic Thread Scheduler for GPGPUs
(2013-01-01)
Huang, Yu-Hao
;
Tseng, Ying-Yu
;
Kuo, Hsien-Kai
;
Yen, Ta-Kan
;
Lai, Bo-Cheng Charles
Modern GPGPUs implement on-chip shared cache to better exploit the data reuse of various general purpose applications. Given the massive amount of concurrent threads in a GPGPU, striking the balance between Data Locality and Load Balance has become a critical design concern. To achieve the best performance, the trade-off between these two factors needs to be performed concurrently. This paper proposes a dynamic thread scheduler which co-optimizes both the data locality and load balance on a GPGPU. The proposed approach is evaluated using three applications with various input datasets. The results show that the proposed approach reduces the overall execution cycles by up to 16% when compared with other approaches concerning only one objective.
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUs
(2013-01-01)
Kuo, Hsien-Kai
;
Yen, Ta-Kan
;
Lai, Bo-Cheng Charles
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
On-chip shared cache is effective to alleviate the memory bottleneck in modern many-core systems, such as GPGPUs. However, when scheduling numerous concurrent threads on a GPGPU, a cache capacity agnostic scheduling scheme could lead to severe cache contention among threads and thus significant performance degradation. Moreover, the diverse working sets in irregular applications make the cache contention issue an even more serious problem. As a result, taking cache capacity into account has become a critical scheduling issue of GPGPUs. This paper formulates a Cache Capacity Aware Thread Scheduling Problem to capture the impact of cache capacity as well as different architectural considerations. With a proof to be NP-hard, this paper has proposed two algorithms to perform the cache capacity aware thread scheduling. The simulation results scheduling scheme can effectively avoid cache contention, and achieve an average of 44.7% cache miss reduction and 28.5% runtime enhancement. The paper also shows the runtime can be enhanced up to 62.5% for more complex applications.