Browsing by Author "Yew, Pen-Chung"

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Adaptive Granularity and Coordinated Management for Timely Prefetching in Multi-Core Systems
(2015)
Chang, Chia-Jung
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Peng, Yin-Chi
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Chen, Chien-Chih
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Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetching to improve the system performance. However, untimely prefetching may pollution caches and resulting into significant performance degradation. In this work, we introduce an Adaptive Granularity and coordinated Prefetching (AGP) that consists of a coarse-grained and fine-grained prefetched mechanism to provide a better caching environment for parallel applications. AGP targets on the degree-adjusting and location-choosing and tries to minimize the influence caused by prefetcher for each core. AGP could produce more timely prefetched requests reducing the cache pollutions and contentions. Across a variety of PARSEC benchmarks, AGP can contribute 6.5% (up to 36%) of performance improvement on a 4-core multicore system compared to the non-prefetching.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013)
Peng, Yin-Chi
;
Chen, Chien-Chih
;
Chang, Chia-Jung
;
Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013-01-01)
Peng, Yin-Chi
;
Chen, Chien-Chih
;
Chang, Chia-Jung
;
Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation
(2014-01-01)
Chen, Chien-Chih
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Peng, Yin-Chi
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Chen, Cheng-Fen
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Wu, Wei-Shan
;
Min, Qinghao
Faced with increasingly large multicore chip designs, architects need fast and accurate simulations for their exploration of design spaces within a limited simulation time budget. In multithreaded applications, threads cannot run simultaneously. Sampling is commonly used to reduce simulation time, but conventional sampling barely detects the instantaneous program variations of synchronization events and the inconsistency between phases of each core. This work proposes a dynamic adjustment and partial sampling technique (DAPs), consisting of aggressive sampling, lazy sampling, and regular sampling, to overcome thread interference in multithreaded applications. Moreover, DAPs partially selects sampling cores to reduce the overhead of sampling inconsistent phases.
Improving Dynamic Binary Optimization Through Early-Exit Guided Code Region Formation
(2013-07-01)
Hsu, Chun-Chen
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Liu, Pangfeng
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Wu, Jan-Jan
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Yew, Pen-Chung
;
Hong, Ding-Yong
Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces. In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multi-threaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NET-variant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of up to 72% (27% on average), and to 49% (23% on average) for IA32 and ARM, respectively.
Selective Profiling for OS Scalability Study on Multicore Systems
(2013)
Chen, Kuo-Yi
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Chang, Yuan-Hao
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Liao, Pei-Shu
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Yew, Pen-Chung
;
Cheng, Sheng-Wei
With more cores becoming available in each future generation of microprocessors (i.e. the well-known Moore\'s Law), scalability is becoming an increasingly important issue. Scalability of the operating system, in particular, is critical to such systems. To study OS scalability and many other issues related to OS performance on multicore systems, software and hardware profilers are indispensable tools. Hardware profilers give detailed performance information on hardware components with minimal overhead, but are difficult to relate the collected information to specific software events. Hence, most of the OS profiling tools are software based. Such profilers often incur significant overheads if more precise measurements are required. The situation is exacerbated further because most of these tools have scalability issue themselves in that their overheads could grow more than proportionately to the number of cores and/or the number of threads in a system. Our results showed that such overheads not only cause much longer execution time (often by orders of magnitude), but also perturb program execution and produce misleading profiling results. In order to mitigate such problems, we propose an approach, called selective profiling, that uses a mix of profiling tools with different levels of precision and overheads to produce the desired results with tolerable overhead. In selective-profiling, potential scalability bottlenecks and hotspots are first identified by low-overhead tracers. More detailed information of the selected bottlenecks and hotspots are then collected by a sampler with more precision but heavier overheads. Since the sampler only focuses on the selected bottlenecks and hotspots instead of the entire program, the overhead can be substantially reduced. Using such an approach on some OS benchmarks, we show that the proposed selective-profiling approach can efficiently identify their scalability bottlenecks with much reduced overheads.