Browsing by Author "Yew, T. R."

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A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
(2014)
Hsieh, E. R.
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Hung, C. M.
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Wang, T. Y.
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Chung, Steve S.
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Huang, R. M.
Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, A(vt), A(gm), in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Liu, C. H.
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Chung, Steve S.
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Huang, R. M.
A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
(2015)
Hsieh, E. R.
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Huang, Z. H.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<50 mu A), fast speed (similar to 20 mu sec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.
The improvement of catalytic efficiency by optimizing Pt on carbon cloth as a cathode of a microbial fuel cell
(2013-10-01)
Yen, S. J.
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Tsai, M. C.
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Wang, Z. C.
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Peng, H. L.
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Tsai, C. H.
This paper presents the performance of Pt deposited by different deposition methods, including electrodeposition, e-gun, and sputtering on a carbon cloth as a cathode in a microbial fuel cell (MFC) system. The results indicate that Pt deposited by electrodeposition exhibits the highest active efficiency on hydrogen electroabsorption. According to XPS fitting results, the amount of Pt (0), zero-valent Pt, existing in Pt deposited on carbon cloth by electrodeposition was larger than that in Pt deposited by e-gun and sputtering. The cyclic voltammogram analyses also show more real active surface area of Pt deposited by electrodeposition, mostly contributed by its smaller particle size/shape and higher catalytic effect. Besides, the total impedance of Pt deposited by electrodeposition was lower than that of Pt deposited by e-gun and sputtering from EIS measurement at 0.1 Hz. Applied to MFC system, the highest power density was manifested and the least Pt loading were observed for the Pt deposited on carbon cloth by electrodeposition. It is therefore can be concluded that the electrodeposited-Pt exhibit superior performance as a cathode for future MFC applications. (C) 2013 Elsevier Ltd. All rights reserved.
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
(2015)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
In this paper, the evolution of BTI induced leakage paths has been evaluated by I-g-RTN technique and demonstrated on HK/MG CMOS devices. First, RTN measurement has been elaborated to identify the location of traps and their correlation to the leakage current. Then, the measured gate current transient can he used to analyze the formation of breakdown path. The results show that the evolution of leakage paths can be divided into three stages, i.e., (I) the early stage- only gate leakage and discrete RTN traps are observed, (2) the middle stage- the traps interacting with the percolation paths and exhibits a multi-level current variation, and (3) the last stage- the formation of breakdown path. These findings provide useful information on the understanding of gate dielectric breakdown in high-k CMOS devices.