Browsing by Author "Yi FanChiang"

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A PITCH BASED VAD ADOPTING QUASI-ANSI 1/3 OCTAVE FILTER BANK WITH 11.3 ms LATENCY FOR MONOSYLLABLE HEARING AIDS
(2013)
Huang, Yi-Cheng
;
Yi FanChiang
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a pitch based voice activity detection (PBVAD) algorithm adopting a quasi-ANSI 1/3 octave filter bank which has low group delay for realistic implementation in hearing aids systems. For compensating the drawback of low resolution resulted from quasi-ASNI filter bank, this pitch based VAD algorithm integrals the features of monosyllable speech such as pitch and corresponding harmonics, onset and time of word length. Simulation results reveal that with more harmonics detection, the accuracy of the proposed PBVAD algorithm improves from 78.9% to 87.7%. Additionally, the proposed VAD algorithm is implemented in ANSI filter bank for comparisons. With the integration of features, the result shows the proposed algorithm can achieve similar VAD accuracy, less than 2.5%, in quasi-ANSI filter bank and ANSI filter bank. Thus, the proposed algorithm can tackle the drawback of quasi-ANSI filter bank and is also suitable for ANSI filter bank. Moreover, the latency incurred by quasi-ANSI filter bank and the proposed VAD algorithm is 11.3ms and this satisfies the requirement of HA systems for practical implementation.
Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing
(2014-08-01)
Yi FanChiang
;
Wei, Cheng-Wen
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Meng, Yi-Le
;
Lin, Yu-Wen
;
Jou, Shyh-Jye
This paper proposes a novel algorithm and architecture for the adaptive feedback cancellation (AFC) based on the pitch and the formant information for hearing aid (HA) applications. The proposed method, named as Pitch based Formant Estimation (PFE-AFC), has significantly low complexity compared to Prediction Error Method AFC (PEM-AFC). The proposed PFE-AFC consists of a forward and a backward path processing. The forward path processing includes a low complexity pitch based formant estimator for decorrelation filter coefficients update and a pitch based voice activity detector for speech detection, which facilitates the feedback cancellation filter in the backward path to reduce feedback component and maintain speech quality. From system point of view, the PFE-AFC has low complexity overhead since it is easy to share computation resource with other components in the HA system, such as noise reduction and auditory compensation. In addition, the PFE-AFC is suitable for hardware implementation owing to its regular structure. Complexity evaluations show that the PFE-AFC has four orders lower complexity than the PEM-AFC. Simulation results show that the PFE-AFC and the PEM-AFC can achieve similar PESQ (perceptual evaluation speech quality) and ASG (added stable gain). Moreover, the proposed PFE-AFC can outperform the conventional AFC.
Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application
(2014-02-01)
Chen, Yu-Jui
;
Wei, Cheng-Wen
;
Yi FanChiang
;
Meng, Yi-Le
;
Huang, Yi-Cheng
This paper presents a low computational complexity hardware-oriented neuromorphic pitch based noise reduction (NR) algorithm and hardware implementation for monosyllable hearing aid system applications. The proposed NR design consists of a pitch-based voice activity detector (pitch-based VAD) for speech detection and a neuromorphic noise attenuator for speech enhancement. The pitch-based VAD is developed on ANSI S1.11 based filter bank architecture and employs the characteristics of monosyllable and nonlinear energy operator (NEO) to improve the accuracy of VAD. The neuromorphic noise attenuator reduces the background noise by using the characteristics of human hearing system and the clues of speech. Simulation results show that the proposed algorithm has better SNR and PESQ performance than other non-pitch based NR algorithms in non-stationary background noise environments. Compared with multiband (mband) spectral subtraction and minimum mean square error (mmse) algorithms, the computational complexity of the proposed algorithm can save 90% computational complexity. The hardware implementation consumes 47.74 mu W at 0.5 V operation with 65 nm HVT standard cell library.