Browsing by Author "Yih, CM"

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A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
(1998-11-01)
Yih, CM
;
Cheng, SM
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the individual contributions of N-it and Q(ox) to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I-G (max). Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices.
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
(1998-11-01)
Yih, CM
;
Cheng, SM
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the individual contributions of N-it and Q(ox) to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I-G (max). Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices.
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
(1997)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
交大名義發表
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
(1999-09-01)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
電子工程學系及電子研究所
In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of hash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N-it) and oxide trap charges (Q(ox)) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N-it and Q(ox), Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation iis the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
(1996)
Yih, CM
;
Chung, SS
;
Hsu, CCH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
(1997-11-01)
Cheng, SM
;
Yih, CM
;
Yeh, JC
;
Kuo, SN
;
Chung, SS
A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N-it) and oxide charge (Q(ox)) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N-it and Q(ox) in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N-it and Q(ox) under various bias stress conditions, such as the hot-electron stress (I-G,I-max), I-B,I-max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N-it and Q(ox) has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, (EPROM)-P-2 cells since the above stress conditions, such as the I-G,I-max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
(1997-11-01)
Cheng, SM
;
Yih, CM
;
Yeh, JC
;
Kuo, SN
;
Chung, SS
A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N-it) and oxide charge (Q(ox)) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N-it and Q(ox) in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N-it and Q(ox) under various bias stress conditions, such as the hot-electron stress (I-G,I-max), I-B,I-max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N-it and Q(ox) has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, (EPROM)-P-2 cells since the above stress conditions, such as the I-G,I-max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
(1999)
Chung, SS
;
Chen, SJ
;
Yih, CM
;
Yang, WJ
;
Chao, TS
In this paper, an accurate criterion has been proposed for reliability evaluation of state-of-the-art deep-submicron S/D extension n-MOSFET's. A new monitor for HC reliability evaluation has been developed using total values of N-it in the effective channel length region, instead of commonly used substrate current(I-B), impact ionization rate (I-D/I-B), or peak/average N-it values. An accurate degradation model has thus been developed based on the N-it distribution and mobility scattering effect. Moreover, this approach has been successfully used to demonstrate the feasibility for gate-engineering studies.
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
(2001-02-01)
Yih, CM
;
Ho, ZH
;
Liang, MS
;
Chung, SS
;
電子工程學系及電子研究所
In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/disharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate, In addition, the present method is very sensitive with capability of measuring ultralow current (<10(-19) A), Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/disharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure.
N-channel versus P-channel flash EEPROM - Which one has better reliabilities
(2001)
Chung, SS
;
Liaw, ST
;
Yih, CM
;
Ho, ZH
;
Lin, CJ
In this paper, a comprehensive study of n- and p-channel flash cells in terms of performance and reliability is presented. In particular, the hot-carrier reliability issues such as disturbs, endurance, in both n- and p-channel flash cells are also investigated. The most serious reliability issue in p-channel flash memory, drain disturb, can be overcome by using DINOR structure. These results can be used as a guideline for designers to choose. Although the n-channel flash cell exhibits higher electron mobilities, the p-channel flash cell is most advantageous with features such as high speed, better reliability, and low power. These meet the scaling trend such that it is a promising candidate for future flash memory applications.
New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors
(2001-01-01)
Chung, SS
;
Chen, SJ
;
Yang, WJ
;
Yih, CM
;
Yang, JJ
In this study, width-dependent hot-carrier degradation in the p-channel metal-oxide-semiconductor held-effect transistors (p-MOSFETs) with shallow-trench-isolation (STI) is presented. Results show an enhanced drain current degradation with reducing the gate width. A new model and mechanism are proposed to explain the width-dependent hot-carrier (HC) degradation for p-MOSFETs. Based on a two-dimensional channel shortening concept, a new model is developed. The mechanical stress enhanced oxide damage at the STI edge, which will induce channel shortening, is the dominant mechanism for the drain current degradation of the devices after hot-carrier stress. This is a crucial issue for present and future complementary metaloxide semiconductor (CMOS) ultra-large-scale integration (ULSI), and in particular for high-density dynamic random-access memory (DRAM), fabricated using STI technologies.
New insight into the degradation mechanism of nitride spacer with different post-oxide in submicron LDD n-MOSFET's
(1998-03-01)
Yih, CM
;
Wang, CL
;
Chung, SS
;
Wu, CC
;
Tan, W
In this paper, the hot carrier degradation mechanisms in lightly-doped drain (LDD) n-MOS devices with silicon nitride spacer have been investigated. A low temperature chemical vapor deposited (CVD) SiO2 oxide is used as a post-oxide between source/drain surface and the nitride spacer. The gated-diode measurement in combination with the gate-induced drain leakage (GIDL) current measurement techniques have been used to analyze the stress-induced interface state and oxide charges. For the first time, it was found that the oxide charge but not the interface state generation in the post oxide will dominate the device drain current degradation. Moreover, the CVD post oxide with N-2 annealing has been proposed which is able to effectively suppress the generation of oxide charges and significantly improve the device hot carrier reliability. The scaling of gate oxide thickness and the optimization of source/drain junction to improve the device reliability are also demonstrated.
Performance and reliability evaluations of P-channel flash memories with different programming schemes
(1997)
Chung, SS
;
Kuo, SN
;
Yih, CM
;
Chao, TS
;
電子工程學系及電子研究所
In this paper, a complete study of the cell reliability based an a unique oxide damage characterization for two different programming schemes of p-channel flash cell will be presented These two programming schemes are Channel Hot Electron (CHE) injection or Band-to-Band (BTB) tunneling induced hot electron injection. Degradation of memory cells after P/E cycles due to the above oxide damages has been identified. It was found that both N-it and Q(ox) will dominate the device degradation during programming. Although p-flash cell has high speed performance by comparing with n-flash cell, extra efforts are needed for designing reliable p-channel flash cell by appropriate drain engineering or related device optimization.