Browsing by Author "Ying, Jen-Cheng"

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Asymmetry dual-LFSR reseeding for low power BIST
(2018-01-01)
Ying, Jen-Cheng
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Tseng, Wang-Dauh
;
Tsai, Wen-Jiin
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資訊工程學系
;
Department of Computer Science
Growing test data volume and excessive test power consumption are two of the major concerns for the industry when testing large integrated circuits. LFSR-decompressor-based compression methods have been widely adopted to reduce test data volume because they can provide high compression ratio. These techniques have been enhanced to address the need for low power as well as low test data volume. The key idea behind these methods is to generate seeds for LFSR reseeding such that the don't-cares in test cubes are filled with proper values to reduce the transition count. This paper presents a LFSR reseeding approach adopting dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Two LFSRs are used to jointly generate test patterns for a given test set to increase the correlation between neighboring bits and thus to reduce the transition count. Experimental results on the ISCAS'89 benchmarks demonstrate that our proposed approach can achieve a better compression ratio than the existing related dual-LFSR scheme while keeping a roughly equal shifting power reduction.
Bipolar Dual-LFSR Reseeding for Low-Power Testing
(2018-01-01)
Ying, Jen-Cheng
;
Tseng, Wang-Dauh
;
Tsai, Wen-Jiin
;
資訊工程學系
;
Department of Computer Science
Large test data volume and excessive test power are two strict challenges for VLSI circuit testing. Built-in self-test (BIST) is recognized as a good solution to the problem of large test data volume. LFSR-decompressor-based compression methods have been widely adopted in BIST to reduce test data volume. The effectiveness of this approach is on the ability to control the generated pseudorandom pattern. This paper adopts dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that it has a significant reduction of data volume and test power using the proposed new Bipolar Dual-LFSR reseeding approach as compared to the existing related dual-LFSR schemes.
Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction
(2019-07-01)
Ying, Jen-Cheng
;
Tseng, Wang-Dauh
;
Tsai, Wen-Jiin
;
資訊工程學系
;
Department of Computer Science
High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a capture power minimization method to disable those scan chains, needless for the target fault detection, during the capture cycle for multi-scan testing. This method combines the scan chain clustering algorithm with the scan chain disabling technique to disable partial scan chains during the capture cycles while keeping the fault coverage unchanged. This method does not induce the capture violation problem nor does it increase the routing overhead. Experimental results for the large ISCAS'89 benchmark circuits show that this method can reduce the capture power by 43.97% averagely.