Browsing by Author "You, KF"

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A new quasi-2-D model for hot-carrier band-to-band tunneling current
(1999-06-01)
You, KF
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A significant mismatch occurs when we predict the gate-induced drain leakage current (GIDL) by using existing one-dimensional (1-D) models, It's found that the gate-induced drain leakage current is attributed to not only the vertical field but also the lateral field near the drain-to-gate overlap region, Therefore, anew quasi-two-dimensional (quasi-2-D) model considering both the lateral and vertical fields for predicting the gate-induced drain leakage current is proposed by using the drain-induced energy-barrier reduction in our model, The calculated results using the developed quasi-2-D model are in good agreement with measured values for a wide range of gate and drain biases, Therefore, the proposed new;model can be used to simulate the hot-carrier band-to-band tunneling current for p-channel flash memory device.
A new simulation model for plasma ashing process-induced oxide degradation in MOSFET
(1998-01-01)
You, KF
;
Chang, MC
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Plasma ashing process-induced oxide damage is studied quantitatively in this paper, To simulate thin gate-oxide damage due to plasma ashing process, a new equivalent circuit model is proposed by including a differential capacitance, a parasitic resistance, an offset flatband voltage, and the effects of feedback on the interface-state and trapped oxide charge densities generated during plasma ashing process, According to this new model, computation of gate oxide charging current is performed by correlating to the latent interface-state density, The test n-MOSFET devices including different antenna-ratios are measured, and excellent agreement is obtained as compared with measured results, Moreover, the deficiency of the previous model is stated and compared, In addition, the effects of substrate doping concentration on plasma-induced oxide damage are also investigated as well as those of plasma ion density, plasma uniformity, thin gate-oxide thickness, Therefore, the relationships between interface state/oxide traps and antenna ratio are linked to provide a guideline for circuit designers and the plasma ashing process-induced damage can be predicted.
A novel two-step etching process for reducing plasma-induced oxide damage
(1996-05-01)
You, KF
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
During plasma etching, a large amount of charging current due to plasma can flow through the gate oxide near the endpoint, resulting in the degradation of thin gate oxide. In this paper, a two-step etching process using reactive ion etching (RIE) following wet etching is proposed to reduce the gate oxide charging current. The characteristics of the proposed process for gate oxide protection are characterized by time-dependent dielectric breakdown (TDDB), high-frequency capacitance-voltage (HFCV), and quasistatic capacitance-voltage (QSCV) measurements. From measurement results, it is shown that degradation of the gate oxide is dramatically eliminated by the proposed two-step etching method as compared with that using pure RIE. Therefore, the proposed two-step etching process can replace the pure dry etching process to reduce the plasma-induced gate oxide damage.