Browsing by Author "You, KS"

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A new fabrication technique for silicon nanowires
(2004-06-01)
Sheu, JT
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Kuo, JM
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You, KS
;
Chen, CC
;
Chang, KM
A new method is proposed for fabricating silicon nanowires (SiNWs) on silicon substrates instead of on SOI wafers, providing a cheaper process; it also enables their electrical properties to be measured easily. Using scanning probe lithography, mask patterns for SiNWs were defined on a (110)-oriented bare silicon wafer. Subsequently silicon nitride spacers were produced and utilized to protect SiNWs during a dry-oxidation process, which was applied to isolate the SiNWs from the substrate. The field induced oxide mask patterns generated with a scanning probe microscope were around 50-60 mn in width, and SiNWs with 34 nm in width and 160 nm in height resulted after wet potassium hydroxide (KOH) orientation-dependent etching at 40degrees for 400 s. SiNWs with line width around 34 mn on the bare silicon wafer were achieved with the scanning probe lithography process and conventional IC processing. (C) 2004 Elsevier B.V. All rights reserved.
An alternative process for silicon nanowire fabrication with SPL and wet etching system
(2004)
Chang, KM
;
You, KS
;
Lin, JH
;
Sheu, JT
;
電子工程學系及電子研究所
Silicon nanowire fabrication of nanoscale dimensions on a single-crystal silicon surface by scanning probe lithography (SPL) and potassium hydroxide (KOH) aqueous wet etching system has proven to be adequate technological processes. Using SPL directly to define patterns on a single-crystal silicon surface showed that the linewidth of similar to50 nm can be further shrunk to similar to20 nm with KOH wet etching and orientation-dependent etching (ODE) processes on (110)-oriented silicon samples. In addition, this lithography technique also showed a great ability to define patterns on fluorocarbon mask layers. This method performed the fine linewidth of silicon nanowires around 20 nm by operating with lower applied voltages and higher scanning speeds (shorter exposure time) with SPL and ODE techniques and KOH wet etching on (100)-oriented silicon samples. These alternative processes provide the capability to fabricate nanoscale structures with high reliability and repeatablility for applications in the nanofields. (C) 2004 The Electrochemical Society.
Nanoflash device with self-aligned double floating gates using scanning probe lithography and tetramethylammonium hydroxide wet etching
(2004-11-01)
Sheu, JT
;
Chen, CC
;
You, KS
;
Tsai, ST
;
材料科學與工程學系奈米科技碩博班
We report a self-aligned technology for nanoflash devices with double floating gates using scanning probe lithography (SPL) technology and anisotropic wet etching. On a (110) SOI silicon wafer, along [001] and [111] directions, a silicon nanowire was generated through local oxidation with SPL followed by wet etching with tetramethylammonium hydroxide solution. Silicon nanowires (SiNW) with profiles of sidewall either sloped or vertical were formed after anisotropic etching in the [001] or [111] direction respectively. After deposition of a polysilicon film on the SiNW with low pressure chemical vapor deposition, nanostructures of a nanoflash device with polysilicon double-floating side gates were obtained along the [111] part of SiNW after reactive ion etching spacer etching. The silicon nanowire channel has a width of 20 nm and a height of 200 rim; the width of the self-aligned floating gate is approximately 40 rim. Silicon nitride was deposited to serve as gate dielectric. The top gate and source-drain aluminum pads were defined by photo litholgraphy. Electrical properties of such a nanoflash device with double-floating side gates are discussed. (C) 2004 American Vacuum Society.
Single-crystal silicon nanostructure fabrication by scanning probe lithography and anisotropic wet etching
(2001)
Chang, KM
;
You, KS
;
Wu, CH
;
Sheu, JT
;
電子工程學系及電子研究所
Silicon nanostructures have been demonstrated by electric-field-enhanced localized oxidation on single crystal silicon wafer using a scanning probe microscope (SPM). In this study, we have demonstrated the use of scanning probe lithography (SPL) and orientation-dependent etching (ODE) can easily obtain nano-wire and nano-gap down to 24nm and 60nm on (110)-oriented silicon substrate. The scanning probe lithography (SPL) provides high resolution, which can be adjusted by tip bias, tip set force, scanning speed, and ambient humidity of environment, without damage in the substrate. The etching process employed the orientation-dependent etching (ODE), because of the etching rate of the (Ill)-plane is slower than any other crystallographic planes such that anisotropic etching profile can be obtained. The experimental samples were hydrogen-passivated by dipping in 10% aqueous HF solution to remove sample native oxide on the surface before SPM localized oxidation process. The SiOx nano-patterns on (110)-oriented silicon substrate were generated by SPM localized oxidation. Then, the etching process employed the ODE with a 34 wt.% aqueous KOH solution. The nano-wire feature size is easily down to 24nm and aspect ratio larger than 4:1. The optimization fine/space nanostructure is about 20 nm/80 nm and the nano-gap is about 60nm. In this study, we also have demonstrated the influence of etching temperature on the feature size of nanostructures with same aspect ratio. At the same etching depth (100nm), the line-width decreases with increasing the etching temperature. The theoretic etching rate and experimental etching rate are proportional to temperature, the higher temperature the higher etching rate.
Single-electron transistor structures based on silicon-on-insulator silicon nanowire fabrication by scanning probe lithography and wet etching
(2002-11-01)
Sheu, JT
;
You, KS
;
Wu, CH
;
Chang, KM
;
電子工程學系及電子研究所
We propose a promising fabrication technology for single-electron transistors based on a silicon-on-insulator (SOI) nanowire fabricated by scanning probe lithography and KOH wet etching. The 10-nm-wide and 10-nm-high silicon nanowire is defined by scanning probe lithography and KOH wet etching process technology. Along the [100] direction on a (100) SOI silicon wafer, local oxidation was performed in ambient using highly doped Si cantilevers with a resistivity of 0.01-0.0025 Omega cm and a commercial atomic force microscope/scanning tunneling microscope instrument. Using the oxide pattern as a Si etching mask, the Si substrate was dipped in aqueous KOH solution, in which unoxidized regions are selectively etched by aqueous KOH orientation-dependent etching. The silicon nanowire was obtained by well-controlled overetching of 34 wt % at 40 degreesC for 50 s. The top gate, back gates and contact pads were defined by photolithography and dry etching. Statistics showing the reproducibility of this technique are also demonstrated. (C) 2002 American Vacuum Society.