Browsing by Author "Yu, Chang-Hung"

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Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET
(2014)
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have reported anomalous electrostatic behaviors in drain-induced-barrier-lowering (DIBL), threshold voltage (VT) roll-off, subthreshold swing (SS), and intrinsic VT variability in GeOI p-MOSFET. The underlying mechanism responsible for these anomalous electrostatic characteristics is attributed to the valence-band offset between Ge channel and Si substrate due to their significant discrepancy in bandgap. This band offset results in an effective built-in forward body bias in GeOI pFET, and leads to different carrier profiles between GeOI pFET and nFET.
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
(2016-01-01)
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity ( monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high R-SD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications.
Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETs
(2014-08-01)
Yu, Chang-Hung
;
Su, Pin
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
This letter reports a built-in effective body-bias effect in ultra-thin-body (UTB) hetero-channel III-V-on-insulator n-MOSFETs. This effect results from the discrepancies in electron affinity and the effective density-of-states of conduction band between the III-V and conventional Si channels. Our study indicates that, in addition to permittivity, it is the built-in effective body-bias effect that determines the drain-induced-barrier-lowering characteristics of the hetero-channel devices. This intrinsic effect has to be considered when one-to-one comparisons among various UTB hetero-channel MOSFETs regarding the electrostatic integrity are made.
Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression
(2015)
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a built-in effective body-bias effect (V-BS,V- eff) in ultra-thin-body and BOX (UTBB) hetero-channel MOSFETs. This effect stems from the discrepancies in the electron affinity, the effective density-of-states, and the band-gap between the high-mobility channel and conventional Si channel. Physical V-BS,V- eff models quantifying this effect are presented for nFET and pFET, respectively. Our study indicates that the DIBL of various hetero-channel devices can be worse than what permittivity predicts because of the built-in forward body-bias effect. Moreover, we have shown that this detrimental effect can be suppressed by the quantum-confinement effect. This effect has to be considered when designing or benchmarking various UTBB hetero-channel MOSFETs.
Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs
(2017-01-01)
Lee, Hung-Yi
;
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
We investigate the analog performance of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) MOSFETs. The device analog metrics including the transconductance (g(m)), output resistance (R-o) and intrinsic gain (g(m) x R-o) for TMD device are investigated using 3D atomistic TCAD simulations. It is shown that bilayer TMD devices exhibit better analog performance compared with monolayer TMD devices. The impacts of different mobility ratios of bilayer TMD devices to monolayer TMD devices are examined.
Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications
(2016-02-01)
Yu, Chang-Hung
;
Fan, Ming-Long
;
Yu, Kuan-Chin
;
Hu, Vita Pi-Ho
;
Su, Pin
For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications.
Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multigate III-V-on-Insulator nMOSFETs
(2016-01-01)
Shen, Hsin-Hung
;
Shen, Shih-Lun
;
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance (C-inv) characteristics of high-mobility multigate III-V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C-inv characteristics stemming from the energy dependence of 1-D density-of-states and significant C-inv degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018-2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge (Q(inv)) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least similar to 3x and similar to 4x, respectively. This paper also suggests that the quantum-capacitance-induced Q(inv) loss can be mitigated by raising the fin aspect ratio of the III-V multigate device.
Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETs
(2012-07-01)
Yu, Chang-Hung
;
Wu, Yu-Sheng
;
Hu, Vita Pi-Ho
;
Su, Pin
;
電子工程學系及電子研究所
This paper investigates the impact of quantum confinement (QC) on the backgate-bias (V-bg) modulated subthreshold and threshold-voltage (V-th) characteristics of ultra-thin-body germanium-on-insulator (UTB GeOI) MOSFETs using an analytical solution of the Schrodinger equation verified with TCAD numerical simulation. Our study indicates that the QC effect reduces the sensitivity of the subthreshold swing to V-bg. In addition, the sensitivity of V-th to V-bg can be enhanced by the QC effect particularly for electrostatically well-behaved UTB MOSFETs with triangular potential well. Aside from that, the sensitivity of V-th roll-off to V-bg is reduced by the QC effect. Since Ge and Si channels exhibit different degrees of QC due to different quantization effective mass, the impact of QC has to be considered when one-to-one comparisons between GeOI and SOI MOSFETs regarding the backgate-bias modulated threshold-voltage and subthreshold characteristics are made. Our study may provide insights for multi-V-th device/circuit designs using advanced UTB GeOI technologies.
Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs
(2012-03-01)
Yu, Chang-Hung
;
Wu, Yu-Sheng
;
Hu, Vita Pi-Ho
;
Su, Pin
;
電子工程學系及電子研究所
This paper investigates the electrostatic integrity (EI) of ultra-thin-body (UTB) germanium-on-insulator (GeOI) and InGaAs-OI n-MOSFETs considering quantum confinement (QC) using a derived analytical solution of Schrodinger equation verified with TCAD numerical simulation. Although the electron conduction path of the high-mobility channel device can be far from the frontgate interface due to high channel permittivity, our study indicates that the quantum confinement effect can move the carrier centroid toward the frontgate and, therefore, improve the subthreshold swing (SS) of the UTB device. Since InGaAs, Ge, and Si channels exhibit different degrees of quantum confinement due to different quantization effective mass, the impact of quantum confinement has to be considered when one-to-one comparisons among UTB InGaAs-OI, GeOI, and SOI MOSFETs regarding the subthreshold swing and electrostatic integrity are made.
Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs
(2016-07)
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed-mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the 6 sigma yield requirement for read static noise margin (RSNM) due to severe metal-gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, R-SD as a major concern of TMDs should be less of an issue for near-/sub-threshold SRAMs for ultra low-power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM). In addition, write-assist techniques (including negative bit-line, boosted word-line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts.
Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs
(2015)
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The intrinsic drain-induced-barrier-lowering (DIBL) characteristics of ultra-thin-body (UTB) MOSFETs with various III-V channel materials (such as GaAs, In0.53Ga0.47As, In0.7Ga0.3As, InAs, In0.2Ga0.8Sb, InSb, etc.) has been investigated and benchmarked with the Si device. Our results indicate that the DIBL of the III-V-on-insulator devices can be worse than what permittivity predicts. The underlying mechanism is proposed. We also show that, with the aid of quantum confinement (along the channel-thickness direction), the DIBL of the III-V devices can be comparable to the Si device.
Investigation of Backgate-Bias Dependence of Intrinsic Variability for UTB Hetero-Channel MOSFETs Considering Quantum Confinement
(2013-01-01)
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Investigation of Backgate-Bias Dependence of Threshold-Voltage Sensitivity to Process and Temperature Variations for Ultra-Thin-Body Hetero-Channel MOSFETs
(2014-03-01)
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the impact of backgate bias (V-bg) on the sensitivity of threshold voltage (V-th) to process and temperature variations for ultra-thin-body (UTB) GeOI and InGaAs-OI MOSFETs. Our study indicates that the quantum-confinement effect significantly suppresses the V-bg dependence of the V-th sensitivity to process and temperature variations. Since Si, Ge, and InGaAs channels exhibit different degrees of quantum confinement, the impact of quantum confinement has to be considered when one-to-one comparisons among hetero-channel UTB devices regarding variability are made. Our study is crucial to the robustness of multi-V-th designs with advanced UTB technologies.
Investigation of Multi-V-th Efficiency for Trigate GeOI p-MOSFETs Using Analytical Solution of 3-D Poisson\'s Equation
(2015-01-01)
Wu, Shu-Hua
;
Yu, Chang-Hung
;
Chiang, Chun-Hsien
;
Su, Pin
;
電子工程學系及電子研究所
This paper provides an analytical subthreshold model for trigate MOSFETs with thin buried oxide (BOX) for multithreshold (multi-V-th) applications. This model shows a fairly good scalability in substrate bias and BOX thickness, which is crucial to the prediction of multi-Vth modulation through BOX. In addition, we demonstrate the application of our model in multi-V-th device design for trigate GeOI p-MOSFETs with the body-effect coefficient (gamma) over a wide range of design space efficiently examined. We have shown an enhanced multi-Vth modulation behavior in trigate GeOI p-MOSFETs. Our study indicates that, for a given subthreshold swing and gamma, the GeOI trigate p-MOSFET can possess a higher fin aspect ratio than the SOI counterpart.
New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
(2015-11-01)
Wu, Shu-Hua
;
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate germanium-on-insulator (GeOI) p-MOSFETs through theoretical calculation by analytical solution of 3-D Poisson's equation corroborated with TCAD numerical simulation. It is found that, relative to the silicon-on-insulator counterpart, there exists a build-in negative substrate bias in the GeOI PFET. This built-in substrate bias, stemming mainly from the large discrepancy in bandgap between Ge and Si, pulls the carriers toward the channel/BOX interface and thus degrades the DIBL of the GeOI PFET beyond what permittivity predicts. This new mechanism has to be considered when designing or benchmarking tri-gate GeOI p-MOSFETs.
Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
(2017-05-01)
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or fewlayer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. Themonolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design.
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
(2016)
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node
(2017-01-01)
Yu, Chang-Hung
;
Zheng, Jun-Teng
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
We comprehensively evaluate and benchmark the performance of pass-transistor logic (PTL) circuits using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 node. Our study indicates that the higher V-T of bilayer TMD devices significantly degrades the performance of single pass-transistor based circuits compared with the monolayer counterparts despite the higher mobility of bilayer TMD devices. The effect can be mitigated by using full transmission gate or providing a complementary path.
Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications
(2016)
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
(2017-01-01)
Wu, Shu-Hua
;
Yu, Chien-Lin
;
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node through numerical simulation corroborated with theoretical calculation. This paper indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. This paper may provide insights for tri-gate device design using III-V high-mobility channel materials.