Browsing by Author "Yu, Chien-Ying"

Now showing 1 - 9 of 9

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
(2009-11-01)
Chen, Tsan-Wen
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Yu, Jui-Yuan
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Yu, Chien-Ying
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 W.
A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications
(2008)
Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Huang, Shang-Bin
;
Chen, Tsan-Wen
;
Chen, Juinn-Ting
This work provides a dual-mode transceiver chipset for wireless body area network (WBAN). The modulation schemes include both MT-CDMA and OFDM. A phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. A rotator-and-synthesizer driven (RSD) frequency pre-calibration with the aid of the PFTCG enables calibration for extended 100ppm frequency error (2.5x of state-of-the-art systems). This chip is manufactured in 90nm standard CMOS process. The supply voltage to the chip core is globally applied at 0.5V with 12 power- and voltage-domain partitions for sleep-active and voltage-scaling management. The PFTCG is operated at 5MHz with RMS jitter 145ps. The transceiver chipset provides maximum 4.85Mbps data rate with 73.7% power reduction in baseband circuit processing.
A 0.6V 200kHz Silicon Oscillator with Temperature Compensation for Wireless Sensing Applications
(2011)
Yu, Chien-Ying
;
Lee, Chen Yi
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a silicon oscillator suitable for low-cost and low-power wireless sensing applications. With the comparisons of ring oscillators in different temperature coefficients, the frequency of an internal ring oscillator is estimated and parameterized by a second-order polynomial. Accordingly, the output clock is compensated in a frequency division fashion. The oscillator is implemented in 90-nm CMOS technology with an area of 0.04mm(2). Operating at 0.6V, the output frequency is within 200+/-1kHz over the temperature range of -25 degrees C to 125 degrees C with power consumption of 48 mu W.
A Frequency Accuracy Enhanced Sub-10 mu W On-Chip Clock Generator for Energy Efficient Crystal-Less Wireless Biotelemetry Applications
(2010)
Sung, Wei-Hao
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Hsu, Shu-Yu
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Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Lee, Chen-Yi
A frequency accuracy enhanced clock generator is proposed for energy efficient crystal-less WBAN system. By applying a self-reference calibration and tracking a remote downlink wireless reference, the robust system clock with +/- 30ppm accuracy against both 20% voltage variation and 75 degrees C temperature variation is developed to enable over-Mbps uplink data transmission. Furthermore, the clock generator based on hysteresis delay cells consumes 7.6 mu W in 5MHz and is able to minimize significant always-on clock source power.
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling
(2012-09-01)
Yu, Chien-Ying
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Yu, Jui-Yuan
;
Lee, Chen-Yi
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電機工程學系
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Department of Electrical and Computer Engineering
"This paper presents a low voltage on-chip oscillator which can compensate process, voltage, and temperature (PVT) variation in an all-digital manner. The relative reference modeling applies a pair of ring oscillators as relative references and estimates period of the internal ring oscillator. The period estimation is parameterized by a second-order polynomial. Accordingly, the oscillator compensates frequency variations in a frequency division fashion. A 1-20 MHz adjustable oscillator is implemented in a 90-nm CMOS technology with 0.04 mm(2) area. The fabricated chips are robust to variations of supply voltage from 0.9 to 1.1 V and temperature range from 0 degrees C to 75 degrees C. The low supply voltage and the small area make it suitable for low-cost and low-power systems."
A Low-Power DCO Using Interlaced Hysteresis Delay Cells
(2012-10-01)
Yu, Chien-Ying
;
Chung, Ching-Che
;
Yu, Chia-Jung
;
Lee, Chen-Yi
;
電機工程學系
This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm(2). The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 mu W at 480- and 200-MHz output, respectively.
A Synchronization Method for Crystal-Less OFDM-Based Wireless Body Area Network Applications
(2009)
Ma, Hsiao-Han
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Yu, Chien-Ying
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Yu, Jui-Yuan
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
A synchronization method includes packet detection and frequency error estimation (PAFEE) is proposed for crystal-less OFDM-based wireless body area network (WBAN) applications to enlarge the frequency error tolerance between the transmitter and receiver. The packet detection method is designed to overcome the large frequency error. The estimated frequency offset (FO) value is provided to a crystal-less tunable clock source. The evaluation platform is the eCrystal WiBoC OFDM-based system. The system overall frequency error tolerance is extended 140x of existing wireless systems. The system is designed and simulated in a 90nm technology with 148.5 mu W computation power and 0.06mm(2) area overhead. Comparing to quartz crystal systems, the overall power reduction is 89.3%, and area reduction is 98.4%.
Absolute time delay generating device
(2010-01-21)
Lee, Chen-Yi
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Yu, Jui-Yuan
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Yu, Chien-Ying
;
Chen, Juinn-Ting
An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.
An eCrystal Oscillator with Self-Calibration Capability
(2009)
Yu, Chien-Ying
;
Yu, Jui-Yuan
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper reports an embedded crystal (eCrystal) oscillator which is capable of compensating process, voltage, and temperature (PVT) variation. The delay behaviors of two different delay cells are exploited for the delay estimation. Then the estimated delay is parameterized by a second order approximated function. According to the estimated delay, the eCrystal oscillator is able to calibrate the frequency error without any external reference. A 40MHz oscillator is implemented in a 90-nm CMOS technology with area of 0.4mm(2) by an all-digital approach. The fabricated chip is measured under supply voltage from 0.9V to 11.1V and temperature range from 0 degrees C to 75 degrees C with active power consumption of 237 mu W.