Browsing by Author "Yu, Dai-Yuan"

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A dual-band four-mode Delta-Sigma frequency synthesizer
(2006)
Chen, Wei-Zen
;
Yu, Dai-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a dualband, four-mode Delta-Sigma frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3(rd) order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 mu sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1 MHz offset are about -114 dBc/Hz and -116 dBe/Hz respectively at 5 GHz and 2.5 GHz; frequency bands. Fabricated in a 0.18- mu m CMOS process, the chip size is 1.95 mm(2). The total power consumption is 19.54 mW from a 1.8 V power supply.
A dual-band four-mode Delta-Sigma frequency synthesizer
(2006-01-01)
Chen, Wei-Zen
;
Yu, Dai-Yuan
;
電機學院
;
College of Electrical and Computer Engineering
This paper describes the design of a dualband, four-mode A-E frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3(rd) order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 g sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-mu g in CMOS process, the chip size is 1.95 mm(2). The total power consumption is 19.54 mW from a 1.8 V power supply.