Browsing by Author "Yu, Guo-Shiuan"

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A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications
(2006-08-01)
Ku, Chun-Wei
;
Cheng, Chao-Chung
;
Yu, Guo-Shiuan
;
Tsai, Min-Chi
;
Chang, Tian-Sheuan
This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications. The whole design is optimized in both the algorithm and architecture levels. In the algorithm level, we propose to remove the area-costly plane mode, and enhance the cost function to reduce hardware cost and to increase the processing speed while provide nearly the same quality. In the architecture design, in additional to the fast module implementation the process is arranged in the macroblock-level pipelining style together with three careful scheduling techniques to avoid the idle cycles and improve the data throughput. The whole codec design only needs 103 K gate count for a core size of 1.28 x 1.28 mm(2) and achieves real-time encoding and decoding at 117 and 25.5 MHz, respectively, when implemented by 0.18-mu m CMOS technology.
A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264
(2006)
Yu, Guo-Shiuan
;
Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264. Instead of just skipping zero block, the proposed design explores the features of CAVLC decoding process to efficient skip possible processes if none needed to be decoded, and can decode multiple symbols in sign and run before stage. The propose design just needs average 90 cycles for one MB decoding, which can meet real time HDTV requirement and saves 64% of cycle count in average when compared with previous design. The hardware cost is about 13192 gates when synthesized at 125 MHz.
Optimal data mapping for motion compensation in H.264 video decoding
(2007)
Yu, Guo-Shiuan
;
Chang, Tian Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Long initial access cycles of SDRAM are the major performance burden of motion compensation in a video decoder. To minimize its effect while improve overall available memory bandwidth, this paper presents an optimal data mapping scheme for motion compensation in H.264 video coding. This scheme allocates the video data into suitable address and bank according to the access characteristics of SDRAM access and address transition in motion compensation. The resulted allocation can reduce the required bandwidth of motion compensation by 36% when compared to the previous design for 525SD video sequences.