Browsing by Author "Yu, H. W."

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Control of metamorphic buffer structure and device performance of InxGa1-xAs epitaxial layers fabricated by metal organic chemical vapor deposition
(2014-12-05)
Nguyen, H. Q.
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Yu, H. W.
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Luc, Q. H.
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Tang, Y. Z.
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Phan, V. T. H.
Using a step-graded (SG) buffer structure via metal-organic chemical vapor deposition, we demonstrate a high suitability of In0.5Ga0.5As epitaxial layers on a GaAs substrate for electronic device application. Taking advantage of the technique\'s precise control, we were able to increase the number of SG layers to achieve a fairly low dislocation density (similar to 10(6)cm(-2)), while keeping each individual SG layer slightly exceeding the critical thickness (similar to 80 nm) for strain relaxation. This met the demanded but contradictory requirements, and even offered excellent scalability by lowering the whole buffer structure down to 2.3 mu m. This scalability overwhelmingly excels the forefront studies. The effects of the SG misfit strain on the crystal quality and surface morphology of In0.5Ga0.5As epitaxial layers were carefully investigated, and were correlated to threading dislocation (TD) blocking mechanisms. From microstructural analyses, TDs can be blocked effectively through self-annihilation reactions, or hindered randomly by misfit dislocation mechanisms. Growth conditions for avoiding phase separation were also explored and identified. The buffer-improved, high-quality In0.5Ga0.5As epitaxial layers enabled a high-performance, metal-oxide-semiconductor capacitor on a GaAs substrate. The devices displayed remarkable capacitance-voltage responses with small frequency dispersion. A promising interface trap density of 3 x 10(12) eV(-1) cm(-2) in a conductance test was also obtained. These electrical performances are competitive to those using lattice-coherent but pricey InGaAs/InP systems.
Effect of graded-temperature arsenic prelayer on quality of GaAs on Ge/Si substrates by metalorganic vapor phase epitaxy
(2011-10-24)
Yu, H. W.
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Chang, E. Y.
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Yamamoto, Y.
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Tillack, B.
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Wang, W. C.
The growth of GaAs epitaxy on Ge/Si substrates with an arsenic prelayer grown with graded temperature ramped from 300 to 420 degrees C is investigated. It is demonstrated that the graded-temperature arsenic prelayer grown on a Ge/Si substrate annealed at 650 degrees C not only improves the surface morphology (roughness: 1.1 nm) but also reduces the anti-phase domains' (APDs) density in GaAs epitaxy (dislocation density: similar to 2 x 10(7) cm(-2)). Moreover, the unwanted interdiffusion between Ge and GaAs epitaxy is suppressed by using the graded-temperature arsenic prelayer due to the low energy of the Ge-As bond and the use of a low V/III ratio of 20. (C) 2011 American Institute of Physics. [doi:10.1063/1.3656737]
Effect of substrate misorientation on the material properties of GaAs/Al(0.3)Ga(0.7)As tunnel diodes
(2010-12-06)
Yu, H. W.
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Chang, E. Y.
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Nguyen, H. Q.
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Chang, J. T.
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Chung, C. C.
The effect of substrate misorientation on the material quality of the N(++)-GaAs/P(++)-AlGaAs tunnel diodes (TDs) grown on these substrates is investigated. It is found that the misorientation influences both surface roughness and interface properties of the N(++)-GaAs/P(++)-AlGaAs TDs. Smooth surface (rms roughness: 1.54 angstrom) and sharp interface for the GaAs/Al(0.3)Ga(0.7)As TDs were obtained when the (100) tilted 10 degrees off toward [111] GaAs substrate was used. Besides, the oxygen content in N(++)-GaAs and P(++)-AlGaAs layers grown on the 10 degrees off GaAs substrates was reduced due to the reduction of sticking coefficient and number of anisotropic sites. (C) 2010 American Institute of Physics. [doi:10.1063/1.3525158]
Effect of substrate misorientation on the material properties of GaAs/Al0.3Ga0.7As tunnel diodes
(2010-12-06)
Yu, H. W.
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Chang, E. Y.
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Nguyen, H. Q.
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Chang, J. T.
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Chung, C. C.
The effect of substrate misorientation on the material quality of the N++-GaAs/P++-AlGaAs tunnel diodes (TDs) grown on these substrates is investigated. It is found that the misorientation influences both surface roughness and interface properties of the N++-GaAs/P++-AlGaAs TDs. Smooth surface (rms roughness: 1.54 angstrom) and sharp interface for the GaAs/Al0.3Ga0.7As TDs were obtained when the (100) tilted 10 degrees off toward [111] GaAs substrate was used. Besides, the oxygen content in N++-GaAs and P++-AlGaAs layers grown on the 10 degrees off GaAs substrates was reduced due to the reduction of sticking coefficient and number of anisotropic sites. (C) 2010 American Institute of Physics. [doi:10.1063/1.3525158]
Growth Parameters Optimization of GaN High Electron Mobility Transistor Structure on Silicon Carbide Substrate
(2014-01-01)
Wong, Y. Y.
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Huang, S. C.
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Huang, W. C.
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Lumbantoruan, F.
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Chiu, Y. S.
High electron mobility transistors heterostructures of AlGaN/GaN were grown by metalorganic chemical vapor deposition system on silicon carbide substrate. The growth parameters such as AlN buffer thickness, AlN spacer growth time and Al content in AlGaN barrier layer were optimized. Moreover, the effects of chamber pressure and V/III ratio at the initial growth state of GaN on film crystal quality were also investigated. The optimized AlGaN/GaN heterostructure has AlN buffer thickness of 120 nm, AlN spacer growth time of 10 s and Al content of 28% in the barrier layer. Furthermore, as a result of using higher chamber pressure and lower V/III, both the GaN crystal quality and electron mobility in the AlGaN/GaN were also significantly improved. After the growth parameter optimization, the GaN (002) and (102) planes exhibited X-ray rocking curve widths of 209 arcsec and 273 arcsec, respectively. Besides, the AlGaN/GaN structure also has an electron mobility of 1832 cm(2)/V-s and a sheet electron density of 1.08 10(13) cm(-2), which yielding a sheet resistance of 316 Omega/sq.
Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET
(2017-11-01)
Singh, S. K.
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Gupta, A.
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Yu, H. W.
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Nagarajan, V.
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Anandan, D.
This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium-arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simulations were performed to investigate the underlying physics. Device on-off (I-on/I-off) ratio was considered as key figure-of-merit (FOM) to improve. It is observed that the off current (I-off) is a weak function of dielectric constant, however, the on current (Ion) increases from 1.51 x 10(-7) A mu m(-1) to 1.79 x 10(-6) A mu m(-1) as the dielectric constant increases from SiO2 to La2O3. It was also observed that as the diameter increases, both Ion and Ioff increases. I-on/I-off ratio is independent for higher channel lengths but as the channel length is reduced below 30 nm, I-off increases causing degradation in Ion/Ioff ratio. Finally, the effect of interface traps was realised on the I-on/I-off ratio. Interface traps impact the flat-band voltage causing a shift in the device performance. It is observed that as the trap density increases, Ioff degrades rapidly by similar to 3 orders in magnitude.
In0.5Ga0.5As-Based Metal-Oxide-Semiconductor Capacitor on GaAs Substrate Using Metal-Organic Chemical Vapor Deposition
(2013-01-01)
Nguyen, H. Q.
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Trinh, H. D.
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Chang, E. Y.
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Lee, C. T.
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Wang, Shin Yuan
We demonstrate the good-performance In0.5Ga0.5As-based metal-oxide-semiconductor capacitor (MOSCAP) on GaAs substrate using metal-organic chemical vapor deposition technique. In0.5Ga0.5As film grown on GaAs substrate is proved to be high quality with threading dislocation density as low as 10(6) cm(-2). The performance of the MOSCAPs is comparable to that of In0.53Ga0.47As/InP-based devices grown by molecular beam epitaxy technique. The devices show a nice capacitance-voltage response, with small frequency dispersion. The parallel conductance contours show the free movement of Fermi level with the gate bias. Acceptable interface trap density D-it values of 5 x 10(11)-2 x 10(12) eV(-1) . cm(-2) in the energy range of 0.64-0.52 eV above the InGaAs valence band maximum in In0.5Ga0.5As/GaAs MOSCAPs obtained by conductance methods were shown.