Browsing by Author "Yu, Jui-Yuan"

Now showing 1 - 18 of 18

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
(2009-11-01)
Chen, Tsan-Wen
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Yu, Jui-Yuan
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Yu, Chien-Ying
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 W.
A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications
(2008)
Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Huang, Shang-Bin
;
Chen, Tsan-Wen
;
Chen, Juinn-Ting
This work provides a dual-mode transceiver chipset for wireless body area network (WBAN). The modulation schemes include both MT-CDMA and OFDM. A phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. A rotator-and-synthesizer driven (RSD) frequency pre-calibration with the aid of the PFTCG enables calibration for extended 100ppm frequency error (2.5x of state-of-the-art systems). This chip is manufactured in 90nm standard CMOS process. The supply voltage to the chip core is globally applied at 0.5V with 12 power- and voltage-domain partitions for sleep-active and voltage-scaling management. The PFTCG is operated at 5MHz with RMS jitter 145ps. The transceiver chipset provides maximum 4.85Mbps data rate with 73.7% power reduction in baseband circuit processing.
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications
(2011-08-01)
Chung, Ching-Che
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Yu, Jui-Yuan
;
Jang, Shiou-Ru
;
Lee, Chen-Yi
;
電機工程學系
This work provides an all-digital smart temperature sensor with dual-mode transceiver chipset for wireless body area network (WBAN). The measurement results show that the proposed temperature sensor achieves a maximum temperature error < 0.6A(0)C within the range from 20A(0)C to 50A(0)C. And a phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. This chip is manufactured on a standard 90 nm CMOS process. The supply voltage to the chip core is globally applied at 0.5 V with 12 power-domain partitions for sleep-active and voltage-scaling management. The transceiver chipset provides maximum 7 Mbps data rate, resulting in 97.7% efficiency improvement in baseband circuit processing.
A dynamic phase-frequency recovery for power reduction in OFDM systems
(2007)
Yang, Mei-Hui
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Yu, Jui-Yuan
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Chen, Juinn-Ting
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
A dynamic phase and frequency recovery (DPR & DFR) is proposed for power reduction and performance improvement. By the DPR, signal sampling rate is reduced from Nyquist rate (or higher) to the symbol rate, resulting in reduced ADC circuit power. By the DFR, data is recovered from less-interfered signals. In the MB-OFDM UWB system, the simulations show that the system improves 2.3 dB SNR and reduce 43.75% ADC power consumption with the proposed techniques.
A Frequency Accuracy Enhanced Sub-10 mu W On-Chip Clock Generator for Energy Efficient Crystal-Less Wireless Biotelemetry Applications
(2010)
Sung, Wei-Hao
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Hsu, Shu-Yu
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Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Lee, Chen-Yi
A frequency accuracy enhanced clock generator is proposed for energy efficient crystal-less WBAN system. By applying a self-reference calibration and tracking a remote downlink wireless reference, the robust system clock with +/- 30ppm accuracy against both 20% voltage variation and 75 degrees C temperature variation is developed to enable over-Mbps uplink data transmission. Furthermore, the clock generator based on hysteresis delay cells consumes 7.6 mu W in 5MHz and is able to minimize significant always-on clock source power.
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling
(2012-09-01)
Yu, Chien-Ying
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Yu, Jui-Yuan
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Lee, Chen-Yi
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電機工程學系
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Department of Electrical and Computer Engineering
"This paper presents a low voltage on-chip oscillator which can compensate process, voltage, and temperature (PVT) variation in an all-digital manner. The relative reference modeling applies a pair of ring oscillators as relative references and estimates period of the internal ring oscillator. The period estimation is parameterized by a second-order polynomial. Accordingly, the oscillator compensates frequency variations in a frequency division fashion. A 1-20 MHz adjustable oscillator is implemented in a 90-nm CMOS technology with 0.04 mm(2) area. The fabricated chips are robust to variations of supply voltage from 0.9 to 1.1 V and temperature range from 0 degrees C to 75 degrees C. The low supply voltage and the small area make it suitable for low-cost and low-power systems."
A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems
(2011-10-01)
Sung, Wei-Hao
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Yu, Jui-Yuan
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Lee, Chen-Yi
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電機工程學系
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Department of Electrical and Computer Engineering
This brief presents a frequency tracking loop (FTL) to realize a crystalless wireless sensor node (WSN) for wireless body area network (WBAN). By tracking a remote wireless RF reference for system clock calibration, the proposed FTL allows WSNs to tolerate a large-frequency error from on-chip CMOS oscillators. Moreover, to achieve energy-efficient transmissions in crystalless, a sufficiently accurate convergence clock is required to enable burst overmegabits-per-second system throughput with minimized operation duty cycle. For the dedicated purpose, a comparison-based binary-search tracking scheme, which ensures accurate and robust convergence against noisy wireless channel, is further developed to manage the operation of FTL. The intermediate frequency back-end part of FTL is implemented in 90-nm CMOS process. Measurement results show that the FTL extends an initial tolerance of system clock error to +/- 3% and achieves a final quartz-crystal comparable +/- 50-ppm accuracy. This enables 4.85-Mb/s wireless links and improves 79% energy efficiency by RF operation-time reduction, giving a power-saved and miniaturized WSN device for WBAN applications.
A Sub-10-mu W Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
(2010-12-01)
Hsu, Shu-Yu
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Yu, Jui-Yuan
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Lee, Chen-Yi
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電機工程學系
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Department of Electrical and Computer Engineering
This brief presents an all digitally controlled oscillator (DCO) design with two newly proposed hysteresis delay cells (HDCs) for wireless body area network applications. According to circuit topologies, the two HDCs are defined as on-off and cascaded HDCs that provide various propagation delay values. These HDCs form a simple oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architecture. Each delay stage provides half of the delay of the previous delay stage in descending order, enabling low-power and small-area features. The P2-DCO is verified in a 90-nm CMOS technology for wide operating frequencies with area of 80 mu m x 80 mu m and least significant bit resolution of 2.05 ps. With a supply voltage of 1.0 V, the measured dynamic power values are 5.4 and 166 mu W at 3.4 and 163.2 MHz, respectively.
A Sub-100 mu W Area-Efficient Digitally-Controlled Oscillator Based on Hysteresis Delay Cell Topologies
(2009)
Chen, Man-Chia
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Yu, Jui-Yuan
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous one in a descending order, resulting in low power and low cost features. A self-calibration method is accompanied to maintain the monotonicity of the P2DCO under PVT variations. The P2DCO is verified in a 90nm CMOS technology. The LSB control word provides a 2.04ps delay resolution. The post-layout simulations show that the dynamic power is 75.9 mu W and 5.2 mu W in the 239.2MHz and 3.89MHz, respectively. The area of the P2DCO is 60*2 mu m(2).
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters
(2011-11-01)
Chen, Tsan-Wen
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Tsai, Ping-Yuan
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Yu, Jui-Yuan
;
Lee, Chen-Yi
;
電機工程學系
Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm(2). The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34 degrees). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 mu W which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15 degrees phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10 degrees phase mismatch, the system EVM of -29.81 dB and ACPR of -34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.
A symbol-rate timing synchronization method for low power wireless OFDM systems
(2008-09-01)
Yu, Jui-Yuan
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Chung, Ching-Che
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Lee, Chen-Yi
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra power consumed in high-rate operations. The proposed PTCG circuits provide the desired clock phase for optimum sampling to improve system performance. Both the DSTC and the PTCG are evaluated in a multibandt OFDM (MB-OFDM) ultra-wide-band system. Simulation results indicate that the overall system performance is improved by 1.7-dB signal-to-noise ratio at a packet error rate of 8% and the total baseband power is reduced by 40%.
A Synchronization Method for Crystal-Less OFDM-Based Wireless Body Area Network Applications
(2009)
Ma, Hsiao-Han
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Yu, Chien-Ying
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Yu, Jui-Yuan
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Lee, Chen-Yi
;
電子工程學系及電子研究所
A synchronization method includes packet detection and frequency error estimation (PAFEE) is proposed for crystal-less OFDM-based wireless body area network (WBAN) applications to enlarge the frequency error tolerance between the transmitter and receiver. The packet detection method is designed to overcome the large frequency error. The estimated frequency offset (FO) value is provided to a crystal-less tunable clock source. The evaluation platform is the eCrystal WiBoC OFDM-based system. The system overall frequency error tolerance is extended 140x of existing wireless systems. The system is designed and simulated in a 90nm technology with 148.5 mu W computation power and 0.06mm(2) area overhead. Comparing to quartz crystal systems, the overall power reduction is 89.3%, and area reduction is 98.4%.
Absolute time delay generating device
(2010-01-21)
Lee, Chen-Yi
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Yu, Jui-Yuan
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Yu, Chien-Ying
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Chen, Juinn-Ting
An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems
(2007)
Yu, Jui-Yuan
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Chen, Juinn-Ting
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Yang, Mei-Hui
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Chung, Ching-Che
;
Lee, Chen-Yi
An all-digital clock generator is designed to enable the clock phase and frequency tuning dynamically during the wireless communications system is in operation. This phase-frequency tunable clock generator (PFTCG) provides 8 clock phases for selection and enables the ADC circuits sampling signals with lower frequency and better sampling phase, resulting in lower power consumption. The PFTCG provides the frequency tuning range +/- 150ppm centered at 5MHz, resulting in high performance due to smaller sampling clock offset. This PFTCG is simulated under the wireless body area network system, and shows a 6.3dB SNR improvement at BER=1 e(-3), and the. hardware is simulated with power 77.56 mu M in the standard process 90nm CMOS technology.
An eCrystal Oscillator with Self-Calibration Capability
(2009)
Yu, Chien-Ying
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Yu, Jui-Yuan
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper reports an embedded crystal (eCrystal) oscillator which is capable of compensating process, voltage, and temperature (PVT) variation. The delay behaviors of two different delay cells are exploited for the delay estimation. Then the estimated delay is parameterized by a second order approximated function. According to the estimated delay, the eCrystal oscillator is able to calibrate the frequency error without any external reference. A 40MHz oscillator is implemented in a 90-nm CMOS technology with area of 0.4mm(2) by an all-digital approach. The fabricated chip is measured under supply voltage from 0.9V to 11.1V and temperature range from 0 degrees C to 75 degrees C with active power consumption of 237 mu W.
Crystal-less Communications Device and Self-Calibrated Embedded Virtual Crystal Clock Generation Method
(2009-11-12)
Lee, Chen-Yi
;
Yu, Jui-Yuan
This invention discloses a crystal-less communication device and self-calibrated embedded virtual crystal clock generation method. In communication systems, the invention proposes a crystal-less scheme in the device for wireless or wired-line communications. The operation concepts are that the transmitter Device-1 provides Device-2 a reference signal, and Device-2 takes this signal to generate a local signal with the similar frequency that has limited frequency error compared with the one from Device-1. This invention is done via the circuit-design methodology, so it can be implemented from any kinds of circuit implementation processes, especially the CMOS process. As a result, the hardware can be designed in the way of highly integration and extremely low cost. Also, this can largely change and improve existing communications design architecture, hardware cost, and hardware area.
DIGITAL DELAY LINE AND APPLICATION THEREOF
(2010-01-21)
LEE, Chen-Yi
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Yu, Jui-Yuan
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Chen, Juinn-Ting
A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.
Estimation of carrier frequency offset with I/Q mismatch using pseudo offset injection in OFDM systems
(2008-04-01)
Sun, Ming-Fu
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Yu, Jui-Yuan
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Hsu, Temg-Yin
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資訊工程學系
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Department of Computer Science
This work presents a novel carrier frequency offset (CFO) estimation algorithm, based on pseudo-CFO (P-CFO), to estimate the CFO value under the conditions of I/Q mismatch for direct conversion structures with 2-dB gain error and 20-deg. phase error in frequency selective fading channels. To circumvent CFO with I/Q mismatch, the proposed P-CFO algorithm rotates three training symbols by adding extra frequency offset into the received sequence to improve CFO estimation. Simulation results indicate that the estimation error of the proposed method is about 0.3 ppm, which is lower than those of two-repeat preamble-based methods. Additionally, the proposed P-CFO algorithm is compatible with the conventional method, and is appropriate for SoC implementation. The proposed scheme is implemented as part of an orthogonal frequency-division multiplexing wireless receiver fabricated in a 0.13-mu m CMOS process with 3.3 x 0.4 mm(2) core area and 10-mW power consumption at 54-Mbits/s data rate.