Browsing by Author "Yu, M. H."

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A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivation
(2012-12-12)
Yu, M. H.
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Liao, M. H.
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Huang, T. C.
;
Wang, L. T.
;
Lee, T. L.
A novel technique to create a suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and the underlying silicon substrate is proposed for the first time to fabricate 28 nm p-metal-oxide-semiconductor field-effect transistors (p-MOSFET). Without Si surface passivation on the ESC, such an ESC structure could achieve a p-FET transconductance (G(m)) gain of 26% higher and a better I-on-I-off performance gain of 8% than that of conventional strained Si p-FETs with the source/drain (S/D) SiGe. Better S/D resistance (R-sd) in the resistance versus gate length plot and improved swing slope of the I-d-V-gs plot indicates higher mobility in the ESC devices. Moreover, the off-state gate current of the ESC structure is also comparable to the conventional ones. From the x-ray photoelectron spectrum analysis, only the Si-O bonding, and no Ge-O bonding at the SiGe/SiO2 interface could account for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm p-MOSFET devices era.
The Strained-SiGe Relaxation Induced Underlying Si Defects Following the Millisecond Annealing for the 32 nm PMOSFETs
(2012)
Yu, M. H.
;
Wang, L. T.
;
Huang, T. C.
;
Lee, T. L.
;
Cheng, H. C.
The formation of the induced defects in the underlying Si substrate from the interaction of the partly relaxed source/drain strained-SiGe layer and subsequent millisecond annealing (MSA) have been systematically explored. It could be found that implantation in the shallower region of the strained-SiGe layer did not form defects in the underlying Si because the remaining strained-SiGe layer was sufficiently thick to resist wafer bending in response to the MSA thermal stress. However, deeper medium-level implantation indeed destroyed the part of the pseudomorphic strained-SiGe and the remaining strained-SiGe was too thin to withstand a significantly compressive stress induced by MSA surface heating and larger coefficient of thermal expansion (CTE) for SiGe than it for Si. Then brittle silicon substrate suffered a great tensile stress to generate numerous defects into plastic deformation. During MSA cooling, the over-bending of the surface SiGe layer contracted more than Si substrate and further results in highly tensile bending. Consequently, high defect density in the underlying Si results in high junction leakage and wafer bending leads to photolithographic limitation. A new approach for modifying the implantation conditions was developed to achieve a relaxation-less strained-SiGe layer and defect-free underlying Si substrate for the 32 nm PMOSFETs. (C) 2011 The Electrochemical Society. [DOI: 10.1149/2.017203jes] All rights reserved.