Browsing by Author "Yu, Ming H."

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A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
(2010)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Kang, Tsung-Kuei
For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Wu, Chun-Yu
;
Kang, Tsung-Kuei
A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.
A Novel Polysilicon Field-Enhanced Nanowire Thin-Film Transistor with the TiN-Hafnia-Nitride-Vacuum-Silicon (THNVAS) Structure for Nonvolatile Memory Applications
(2012-07-01)
Wu, Chun-Yu
;
Liao, Ta-Chuan
;
Liu, Yen-Ting
;
Yu, Ming H.
;
Cheng, Huang-Chung
A novel poly-Si field-enhanced nanowire (FEN) TFT memory with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure fabricated simply via a sidewall spacer formation has been presented. The THNVAS devices with superior memory performance were demonstrated by introducing the hafnia as blocking oxide and the vacuum, the lowest-k in nature, as tunneling layer. According to the simulation results, the memory device with oxide/nitride/vacuum gate dielectric exhibited a higher local electric-field of 4.72 x 10(7) V/cm as compared to 2.55 x 10(7) V/cm for the conventional oxide/nitride/oxide counterpart. In addition, the electric-field of tunneling layer could be further increased to 7.06 x 10(7) V/cm while the blocking oxide was substituted for hafnia. The experimental data showed that THNVAS possessed a greater threshold voltage shift of 3.75 V in 10 ms at V-GS = 12 V, whereas the shift only 2.5 V for THNOS ones. These considerable improvements for THNVAS devices could be attributed to the evident field enhancement across the vacuum tunneling layer. Furthermore, owing to the empty feature of vacuum tunneling layer, the THNVAS demonstrated much-improved endurance performance and preferable data retention property. Hence, such excellent characteristics of THNVAS will be an attractive nonvolatile memory for future system-on-panel and 3-D Flash applications.
Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structure
(2011-08-01)
Wu, Chun-Yu
;
Liu, Yen-Ting
;
Liao, Ta-Chuan
;
Yu, Ming H.
;
Cheng, Huang-Chung
High-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.
Novel gate-all-around poly-Si TFTs with multiple nanowire channels
(2008-08-01)
Liao, Ta-Chuan
;
Tu, Shih-Wei
;
Yu, Ming H.
;
Lin, Wei-Kai
;
Liu, Cheng-Chin
The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (T(Fin)/W(Fin)), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio (> 10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits.
Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond
(2006)
Yu, Ming H.
;
Li, J. H.
;
Lin, H. H.
;
Chen, C. H.
;
Ku, K. C.
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved.