Browsing by Author "Yu, SM"
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Item type:Item, A numerical iterative method for solving Schrodinger and Poisson equations in nanoscale single, double and surrounding gate metal-oxide-semiconductor structures(2005-07-01) ;Li, YM ;Yu, SM ;友訊交大聯合研發中心D Link NCTU Joint Res CtrNumerical solution of the Schrodinger and Poisson equations (SPEs) plays an important role in semiconductor simulation. We in this paper present a robust iterative method to compute the self-consistent solution of the SPEs in nanoscale metal-oxide-semiconductor (MOS) structures. Based on the global convergence of the monotone iterative (Ml) method in solving the quantum corrected nonlinear Poisson equation (PE), this iterative method is successfully implemented and tested on the single-, double-, and surrounding-gate (SG, DG, and AG) MOS structures. Compared with other approaches, various numerical simulations are demonstrated to show the accuracy and efficiency of the method. (c) 2005 Elsevier B.V All rights reserved.Item type:Item, A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation(2005-03-01) ;Li, YM ;Yu, SM ;友訊交大聯合研發中心D Link NCTU Joint Res CtrWe propose in this paper a quantum correction transport model for nanoscale double-gate metal-oxide-semiconductor field effect transistor (MOSFET) device simulation. Based on adaptive finite volume, parallel domain decomposition, monotone iterative, and a posteriori error estimation methods, the model is solved numerically on a PC-based Linux cluster with MPI libraries. Quantum mechanical effect plays an important role in semiconductor nanoscale device simulation. To model this effect. a physical-based quantum correction equation is derived and solved with the hydrodynamic transport model. Numerical calculation of the quantum correction transport model is implemented with the parallel adaptive finite volume method which has recently been proposed by us in deep-submicron semiconductor device simulation. A 20 nm double-gate MOSFET is simulated with the developed quantum transport model and computational technique. Compared with a classical transport model. it is found that this model can account for the quantum mechanical effects of the nanoscale double-gate MOSFET quantitatively. Various biasing conditions have been verified on the simulated device to demonstrate its accuracy. Furthermore. for the same tested problem, the parallel adaptive computation shows very good computational performance in terms of the mesh refinements, the parallel speedup, the load-balancing, and the efficiency. (C) 2004 Elsevier B.V. All rights reserved.Item type:Item, A two-dimensional quantum transport simulation of nanoscale double-gate MOSFETs using parallel adaptive technique(2004-07-01) ;Li, YM ;Yu, SM ;奈米中心 ;友訊交大聯合研發中心Nano Facility CenterIn this paper we apply a parallel adaptive solution algorithm to simulate nanoscale double-gate metal-oxide-semiconductor field effect transistors (MOSFETs) on a personal computer (PC)-based Linux cluster with the message passing interface (MPI) libraries. Based on a posteriori error estimation, the triangular mesh generation, the adaptive finite volume method, the monotone iterative method, and the parallel domain decomposition algorithm, a set of two-dimensional quantum correction hydrodynamic (HD) equations is solved numerically on our constructed cluster system. This parallel adaptive simulation methodology with 1-irregular mesh was successfully developed and applied to deep-submicron semiconductor device simulation in our recent work. A 10 nm n-type double-gate MOSFET is simulated with the developed parallel adaptive simulator. In terms of physical quantities and refined adaptive mesh, simulation results demonstrate very good accuracy and computational efficiency. Benchmark results, such as load-balancing, speedup, and parallel efficiency are achieved and exhibit excellent, parallel performance. On a 16 nodes PC-based Linux cluster, the maximum difference among CPUs is less than 6%. A 12.8 times speedup and 80% parallel efficiency are simultaneously attained with respect to different simulation cases.Item type:Item, A unified quantum correction model for nanoscale single- and double-gate MOSFETs under inversion conditions(2004-08-01) ;Li, YM ;Yu, SM ;友訊交大聯合研發中心D Link NCTU Joint Res CtrIn this paper a unified quantum correction charge model for nanoscale single- and double-gate MOS structures is presented. Based on the numerical solution of Schrodinger-Poisson equations, the developed quantum correction charge model is mainly optimized with respect to (i) the left and right positions of the charge concentration peak, (ii) the maximum of the charge concentration, (iii) the total inversion charge sheet density, and (iv) the average inversion charge depth, respectively. For nanoscale single- and double-gate MOS structures, this model predicts inversion layer electron density for various oxide thicknesses, silicon film thicknesses, and applied voltages. Compared to the Schrodinger-Poisson results, our model prediction is within 2.5% of accuracy for both the single- and double gate MOS structures on average. This quantum correction model has continuous derivatives and is therefore amenable to a device simulator.Item type:Item, Computer simulation of germanium nanowire field effect transistors(2005) ;Li, YM ;Chou, HM ;Lee, BS ;Lu, CSYu, SMIn this paper, electrical characteristics of germanium (Ge) nanowire field effect transistors (FETs) are computationally investigated. A calibrated three-dimensional (3D) density-gradient simulation is performed to explore the electrical characteristics of Ge omega-shaped-gate FETs. The examined nanodevices are with a 70% gate coverage ratio. By evaluating the threshold voltage roll-off, the transfer characteristics, and the leakage current, our numerical results have shown that the Ge nanowire FET has potentially higher driving-capability than that of the silicon (Si) one. Due to good channel controllability of the omega-shaped-gate FET with the 70% gate coverage ratio, compared with the Si nanowire FET, the high mobility Ge nanowire FET significantly suppresses the effect of band-gap narrowing on the transport characteristics. Leakage current of the Ge nanowire FET depends upon the thickness of the gate channel film. A thinner Ge film leads to a lower leakage current. Preliminary numerical study on the Ge Nanowire FET with a propoer selection on gate material provides interesting results for the design and fabrication of high performance nanodevices in nanoelectronics era.Item type:Item, Quantum mechanical corrected simulation program with integrated circuit emphasis model for simulation of ultrathin oxide metal-oxide-semiconductor field effect transistor gate tunneling current(2005-04-01) ;Li, YM ;Yu, SM ;Lee, JW ;友訊交大聯合研發中心D Link NCTU Joint Res CtrIn this paper we present a quantum mechanical corrected gate tunneling current model for simulating ultrathin oxide metal-oxide-semiconductor (MOS) devices. By approximating the physically based Esaki-Tsu tunneling formula and explicitly modeling the classical (CL) and quantum mechanical (QM) corrected surface potential, this model successfully predicts the gate tunneling current for ultrathin oxide MOS samples under different applied biases. Simply assuming all tunneling electrons have the same kinetic energy, the Esaki-Tsu tunneling formula is first simplified so that it can be solved without encountering numerical integral. problems. Numerical solutions of the classical Poisson equation and Schrodinger-Poisson equations are then used to analytically express the CL and QM corrected surface potentials explicitly in terms of substrate doping, thickness of the gate oxide (T(ox)(ox)(), and applied bias. The full explicit, physical-based, and QM corrected gate tunneling current model quantitatively shows good agreement with the technology computer-aided design (TCAD) simulation. Compared with the measured gate tunneling current from fabricated 0.12 mm n-type Metal-Oxide-Semiconductor Field Effect Transistors (NMOSFETs) with three different thicknesses of gate oxide, T) = 1, 1.2 and 1.5 nm, the QM corrected gate tunneling current model shows good accuracy for various ultrathin oxide samples under different biases. However, the gate tunneling current model with the CL surface potential results in one order of magnitude underestimation in comparison with the measured data. We implement the gate tunneling current model into the simulation program with integrated circuit emphasis (SPICE) simulator and perform a DC simulation. Simulated results preliminarily show the effect of the gate leakage current on the drain current without any numerical convergence problem.Item type:Item, Simulation of electrical characteristics of surrounding- and omega-shaped-gate nanowire FinFETs(2004) ;Tang, CS ;Yu, SM ;Chou, HM ;Lee, JWLi, YMIn this paper, electrical characteristics of sub-10 not nanowire FinFETs are investigated using a three-dimensional (3D) quantum correction simulation. Two different nanowire FinFETs, surrounding-gate FinFET and omega-shaped-gate one, are simulated with density-gradient-based model and compared in terms of on/off current, turn-on resistance, gate capacitance. It is found that the characteristic difference between surrounding-gate FinFET and omega-shaped-gate FinFET with a 70% coverage is insignificant. However, the former possesses better DIBL effect than that latter with different coverage ratios. Our examination presented here is useful in the fabrication of omega-shaped nanowire FinFETs.