Browsing by Author "Yu, Sheng-Wen"

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16-GHz mHEMT Double-Quadrature Gilbert Down-Conversion Mixer With Polyphase Filters
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 16-GHz double-quadrature very low IF down conversion mixer with polyphase filters is demonstrated using 0.15-nm metamorphic high electron mobility transistor (mHEMT) technology. Due to the hgih cut-off frequency of mHEMT device, the image rejection Gilbert mixer works at 16 GHz. The polyphase filters are employed to generate differential quadrature signals and eliminate the image signal at RF/LO stages and IF stage, respectively, in the double quarture configuration. When RF and LO frequencies are designed around 16 GHz and an IF frequency is 32 MHz, The double-quadrature Gilbert down-converter has 32-dB image rejection ratio, 1.7-dB conversion gain, -5-dBm IP1dB, and 5-dBm IIP3. The die size is 3.0 mm x 3.2 mm.
17-GHz pHEMT Gilbert Single-Quadrature Downconverter With Polyphase Filters for Image Rejection
(2010-01-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 17-GHz Gilbert single-quadrature down-converter (SQDC) with polyphase filters is successfully demonstrated using 0.15-mu m pseudomorphic high electron mobility transistor (pHEMT) technology for the first time to the best of our knowledge. Thanks to the semi-insulating GaAs substrate and an advanced technology, the image rejection Gilbert mixer works well at high frequencies. A polyphase filter at the LO stage is employed to generate precisely differential quadrature signals and a four-stage polyphase filter at the IF stage can filter out the unwanted image signal to achieve image rejection. From 10-MHz to 90-MHz IF frequencies, a 30-dB image rejection ratio is achieved when RF and LO frequencies are designed around 17 GHz. The Gilbert SQDC has a 5.5-dB conversion gain, 0-dBm IP1db, and 16-dBm IIP3.
2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver-Hartley Image-Rejection Techniques
(2009-03-01)
Meng, Chin-Chun
;
Wu, Tzung-Han
;
Syu, Jin-Siang
;
Yu, Sheng-Wen
;
Tsung, Kuan-Chang
A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-mu m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture.
2.4/5.7-GHz Dual-Band Dual-Conversion Architecture With Correlated LO Signal Generators
(2009)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Wu, Tzung-Han
;
Huang, Guo-Wei
A 2.4/5.7-GHz dual-band dual-conversion downconverter is demonstrated using 0.35-mu m SiGe hetero-junction bipolar transistor (HBT) technology. This downconverter employs a complex dual-conversion system and a complex filter to reject the first and second image signals, respectively. The LO(1) frequency is 2.5 times the LO(2) frequency and is generated by a divide-by-two divider, a frequency doubler and a single-sideband up-converter. As a result, the correlated LO signals maintain excellent image-rejection performance of the dual-conversion system while only one LO input is needed. The downconverter achieves a 40/39-dB image-rejection ratio of the first image and a 44/46-dB image-rejection ratio of the second image for 2.4/5.7-GHz modes, respectively.
A Chebyshev-Response Step-Impedance Phase-Inverter Rat-Race Coupler Directly on Lossy Silicon Substrate and Its Gilbert Mixer Application
(2011-04)
Wei, Hung-Ju
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Chang, Chia-Hung
;
電機工程學系
This paper focuses on the analysis and the design methodology of the step-impedance phase-inverter rat-race coupler on a silicon-based process. The issues of impedance limitation and bandwidth are discussed in detail. Our proposed concept utilizes a high silicon dielectric constant, phase-inverter structure, step-impedance technique, and Chebyshev response to make the rat-race coupler more compact (similar to 64 reduction) and highly balanced over a wide operating bandwidth. Moreover, the inter-digital coplanar stripline used in the step-impedance section effectively reduces the characteristic impedance of the transmission line for large size shrinkage and insertion-loss reduction. The demonstrated step-impedance rat-race coupler directly on silicon substrate has 6- similar to 7-dB insertion loss from 5 to 15 GHz and small variations in amplitude/phase balance. Compared with our previous work, the proposed rat-race coupler achieves a 3-dB improvement in the insertion loss. Thus, a 0.13-mu m CMOS Gilbert down-converter with a miniature phase-inverter rat-race coupler at the RF path for wideband single-to-differential signal conversion achieves a noise figure of 16 dB.
A Chebyshev-Response Step-Impedance Phase-Inverter Rat-Race Coupler Directly on Lossy Silicon Substrate and Its Gilbert Mixer Application
(2011-04)
Wei, Hung-Ju
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Chang, Chia-Hung
;
電機工程學系
This paper focuses on the analysis and the design methodology of the step-impedance phase-inverter rat-race coupler on a silicon-based process. The issues of impedance limitation and bandwidth are discussed in detail. Our proposed concept utilizes a high silicon dielectric constant, phase-inverter structure, step-impedance technique, and Chebyshev response to make the rat-race coupler more compact (similar to 64 reduction) and highly balanced over a wide operating bandwidth. Moreover, the inter-digital coplanar stripline used in the step-impedance section effectively reduces the characteristic impedance of the transmission line for large size shrinkage and insertion-loss reduction. The demonstrated step-impedance rat-race coupler directly on silicon substrate has 6- similar to 7-dB insertion loss from 5 to 15 GHz and small variations in amplitude/phase balance. Compared with our previous work, the proposed rat-race coupler achieves a 3-dB improvement in the insertion loss. Thus, a 0.13-mu m CMOS Gilbert down-converter with a miniature phase-inverter rat-race coupler at the RF path for wideband single-to-differential signal conversion achieves a noise figure of 16 dB.
Broadband CMOS Gilbert Down-Converter Utilizing a Low-Loss Step-Impedance Rat-Race Coupler
(2009)
Wei, Hung-Ju
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
電信工程研究所
;
Institute of Communications Engineering
A Broadband Gilbert Down-Converter with step-impedance rat-race coupler is demonstrated using 0.13 mu m standard CMOS technology. The proposed method utilizes higher effective dielectric-constant, phase-inverter and step-impedance techniques simultaneously to make the rat-race coupler more compact (similar to 64% reduction) and phase-balanced over a wide operating bandwidth. The down-converter has NF of 16 dB and LO-to-RF isolation of better than 35 dB. The mixer core consumes 2.9 mA at V(dd)=1.8 V.