Browsing by Author "Yu, Tsung-Han"

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A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
(2012-09-01)
Yu, Tsung-Han
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Yang, Chia-Hsiang
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Cabric, Danijela
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Markovic, Dejan
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電子工程學系及電子研究所
"A digital baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm in 65-nm(2) CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability >= 0.9 and false-alarm probability <= 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22x reduction in power per sensing bandwidth compared with prior work."
An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing
(2011)
Yu, Tsung-Han
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Yang, Chia-Hsiang
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Markovic, Dejan
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Cabric, Danijela
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電子工程學系及電子研究所
Spectrum sensing over a wide bandwidth increases the probability of finding unutilized spectrum for cognitive radios. However, energy-efficient VLSI realization of wideband sensing algorithms is challenging due to complex signal processing and real-time requirement. In addition, strong primary users introduce spectral leakage in adjacent unused bands, resulting in sensing performance degradation. To address these challenges, we propose a cascaded filter-bank channelization scheme and its re-configurable VLSI architecture that can be optimized for power, area, sensing time, and detection performance. In addition, the spectral leakage due to strong interference is compensated with an interference cancellation method. Compared to the conventional PSD-based energy detection, the proposed channelization scheme supports reliable wideband signal detection with 2.5x less power. Given a 0.5ms sensing time under 30-dB adjacent-band interference-to-noise ratio, a 30x sensing-time improvement is achieved while maintaining a false-alarm probability of 0.1 and a detection probability of 0.9. The energy efficiency is improved from lower power consumption and reduced sensing time.
Backside-Process-Induced Junction Leakage and Process Improvement of Cu TSV Based on Cu/Sn and BCB Hybrid Bonding
(2013-03-01)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Yu, Tsung-Han
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Chiang, Cheng-Hao
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Chen, Kuan-Neng
Wafer-level 3-D integration using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding is investigated with electrical leakage current. With the well-fabricated Cu TSVs and Cu/Sn bond structures, the leakage current path in this scheme due to backside process was found, and the corresponding mechanism is discussed. The leakage current can be solved by the modified backside process. The improved 3-D integration scheme shows extremely low leakage current and no visible defects inside Cu TSV.
Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding
(2013)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chiang, Cheng-Hao
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Fu, Huan-Chun
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250 degrees C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Microlens array by ink-jet technology for LCD backlight applications
(2008)
Hung, Chien-Hsiang
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Yu, Tsung-Han
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Cheng, Jung-An
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Chang, Chi-Hsien
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Hsiau, Yi-Hau
This research uses Ink-jet printer process to fabricate microlens on the bottom of a LGP in a fast and cost-effective way. Compared with typical dot printing method, Ink-jet printing is able to save 50% material consumption. In addition, the microlens with UV-curable epoxy could be well controlled in the radius, contact angle and arbitrary arrangement. A 20x20cm(2) LGP can be fabricated with desired microlens pattern within 10 seconds, which exhibits a potential to apply ink-jet process upon the high-speed mass production.
Microlens Arrays by Direct-Writing Inkjet Print for LCD Backlighting Applications
(2009-04-01)
Tien, Chun-Hao
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Hung, Chien-Hsiang
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Yu, Tsung-Han
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光電工程學系
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顯示科技研究所
In this paper, we demonstrated the Inkjet print method to fabricate a ultraviolet (UV)-curable epoxy microlens deflecting array with controllable curvature and filling factor, by which a 7-in light guide plate with 82% uniformity and 70% light efficiency was successfully implemented. The microlenses can be directly formed by plastic discharged by inkjet head, eliminating the need for molds and slashing development time. Proposed method will certainly has a promising impact on rapid proto-typing and other specialized microfeatures due to its simplicity and versatility.
Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application
(2015-06-01)
Chang, Yao-Yen
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Ko, Cheng-Ta
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Yu, Tsung-Han
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Hsieh, Yu-Sheng
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Chen, Kuan-Neng
Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson\'s equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 mu m. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (vertical bar V-ow vertical bar = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Q(ot) engineering in TSV oxide liner, neither considerations of the V-FB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example
(2012-03-01)
Yang, Chia-Hsiang
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Yu, Tsung-Han
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Markovic, Dejan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 x 1.1 mm(2) and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.