Browsing by Author "Yu, Yen-Ting"

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3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
(2011)
Chan, Cheng-Chi
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Yu, Yen-Ting
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
During the billion transistor era, 3D stacking offers an attractive solution for the difficulties resulting from large-scale design complexities. Moreover, 3D stacking can benefit performance, power, bandwidth, footprint, and heterogeneous technology mixing. However, before adopting the 3D design strategy, this study seeks to understand how much cost is required to trade these benefits. This paper proposes a 3D IC cost evaluation framework based on fast tier number estimation Using a reformulated Rent's rule, this study efficiently determines the number k of tiers to minimize the through-silicon via count and then automatically partitions a gate-level netlist into k tiers to minimize the total cost. This study conducted experiments on eight industrial test cases to show cost efficiency and effectiveness. Moreover, results prove that the reformulated Rent's rule indicates a strong correlation between the tier number and through-silicon via usage.
Accurate Process-Hotspot Detection Using Critical Design Rule Extraction
(2012)
Yu, Yen-Ting
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Chan, Ya-Chung
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Sinha, Subarna
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Jiang, Iris Hui-Ru
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Chiang, Charles
In advanced fabrication technology, the sub-wavelength lithography gap causes unwanted layout distortions. Even if a layout passes design rule checking (DRC), it still might contain process hotspots, which are sensitive to the lithographic process. Hence, process-hotspot detection has become a crucial issue. In this paper, we propose an accurate process-hotspot detection framework. Unlike existing DRC-based works, we extract only critical design rules to express the topological features of hotspot patterns. We adopt a two-stage filtering process to locate all hotspots accurately and efficiently. Compared with state-of-the-art DRC-based works, our results show that our approach can reach 100% success rate with significant speedups.
Configurable Rectilinear Steiner Tree Construction for SoC and Nano Technologies
(2008)
Jiang, Iris Hui-Ru
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Yu, Yen-Ting
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The rectilinear Steiner minimal tree (RSMT) problem is essential in physical design. Moreover, the variant constraints for fabrication issues, including obstacle avoidance, multiple routing layers, layer-specific routing directions, cannot be ignored during RSMT construction for modern SoC and nano technologies. This paper proposes a construction-by-correction approach for obstacle-avoiding preferred direction rectilinear Steiner tree construction. Experimental results show that our algorithm is promising and outperforms the state-of-the-art works.
DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification
(2014)
Yu, Yen-Ting
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Jiang, Iris Hui-Ru
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Zhang, Yumin
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Chiang, Charles
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交大名義發表
To improve the yield in current manufacturing processes, the problematic layout configurations, so-called process-hotspots, should be detected and replaced with yield friendly patterns. A hotspot pattern with edge tolerances and incomplete specifications, where edges may vary in a certain range and any layout configurations may exist in its ambit regions, can sufficiently and generally represent a process-hotspot. This type of hotspots, however, cannot be efficiently or correctly detected by using the state-of-the-art string-matching-based method. In this paper, we present an accurate and efficient DRC-based hotspot detection framework to handle hotspot patterns with edge tolerances and incomplete specifications. Unlike existing DRC-based work, which handles only completely specified patterns, we extract critical design rules to represent all possible topologies of hotspot patterns with edge tolerances and incomplete specifications. We further order these rules to iteratively reduce the search regions of a layout during design rule checking. Then, we apply longest common subsequence and linear scan to locate all hotspots accurately and efficiently. Compared with the state-of-the-art work, experimental results show that our approach can reach promising success rates with significant speedups.
iClaire: A Fast and General Layout Pattern Classification Algorithm
(2017-01-01)
Chang, Wei-Chun
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Jiang, Iris Hui-Ru
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Yu, Yen-Ting
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Liu, Wei-Fang
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電子工程學系及電子研究所
Layout pattern classification, which groups similar layout clips into clusters, underlies a variety of design for manufacturability (DFM) applications such as hotspot library generation, hierarchical data storage, and yield optimization speedup. The key challenges of layout pattern classification are clip representation and clip clustering, while the mutually conflicting concerns are efficiency and solution quality (in terms of cluster count). In this paper, we present a fast and general layout pattern classification algorithm. Our simple but general clip representation captures both topology and density; we can handle not only rigid area match or edge displacement constraints but also variant edge tolerances and don't care regions. On the other hand, for achieving a small cluster count, our clip clustering is guided by the natural grouping structure of layout clips. Our experiments are conducted on 2016 CAD contest at ICCAD benchmark suite; our results show that our algorithm outperforms the reference solution and all contest winning teams, delivering the smallest cluster count, fastest runtime, and 100% validity. In addition to the good solution quality, the interplay between adopted simple and easily manipulated data structures and our algorithm makes it fast and viable to be incorporated into practical DFM flows.
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
(2013)
Yu, Yen-Ting
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Lin, Geng-He
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Jiang, Iris Hui-Ru
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Chiang, Charles
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電子工程學系及電子研究所
Because of the widening sub-wavelength lithography gap in advanced fabrication technology, lithography hotspot detection has become an essential task in design for manufacturability. Current state-of-the-art works unite pattern matching and machine learning engines. Unlike them, we fully exploit the strengths of machine learning using novel techniques. By combing topological classification and critical feature extraction, our hotspot detection framework achieves very high accuracy. Furthermore, to speed up the evaluation, we verify only possible layout clips instead of full-layout scanning. After detection, we filter hotspots to reduce the false alarm. Experimental results show that the proposed framework is very accurate and demonstrates a rapid training convergence. Moreover, our framework outperforms the 2012 CAD Contest at ICCAD winner on accuracy and false alarm.
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
(2015-03-01)
Yu, Yen-Ting
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Lin, Geng-He
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Jiang, Iris Hui-Ru
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Chiang, Charles
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電子工程學系及電子研究所
Because of the widening sub-wavelength lithography gap in advanced fabrication technology, lithography hotspot detection has become an essential task in design for manufacturability. Unlike current state-of-the-art works, which unite pattern matching and machine-learning engines, we fully exploit the strengths of machine learning using novel techniques. By combing topological classification and critical feature extraction, our hotspot detection framework achieves very high accuracy. Furthermore, to speed-up the evaluation, we verify only possible layout clips instead of full-layout scanning. We utilize feedback learning and present redundant clip removal to reduce the false alarm. Experimental results show that the proposed framework is very accurate and demonstrates a rapid training convergence. Moreover, our framework outperforms the 2012 CAD contest at International Conference on Computer-Aided Design (ICCAD) winner on accuracy and false alarm.
UNIFICATION OF OBSTACLE-AVOIDING RECTILINEAR STEINER TREE CONSTRUCTION
(2008)
Jiang, Iris Hui-Ru
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Lin, Shung-Wei
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Yu, Yen-Ting
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Multi-layer obstacle-avoiding rectilinear Steiner tree construction is an essential problem in physical design for advanced SoC and nano technologies. This paper unifies obstacle-avoiding rectilinear Steiner tree construction either for single or for multiple routing layers. Experimental results show that our algorithm outperforms the state-of-the-art works for both cases.