Browsing by Author "Yu, Yuan-Chu"

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A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application
(2006)
Lin, Chin-Teng
;
Yu, Yuan-Chu
;
Van, Lan-Da
;
資訊工程學系
;
電控工程研究所
In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT (R8-FFT) unit and an efficienet data-swapping method based output buffer unit The whole chip systematic performance concerning about the area, power, latency and pending cycles for the application of IEEE 802.11a WLAN standard has been analyzed. The proposed R8-FFT unit utilizing the symmetry property of the matrix decomposition achieves half computation-complexity and less power consumption compared with the recently proposed FFT/IFFT designs, On the other hand, applying the proposed data-swapping method, a low-cost and low-power output buffer can be obtained, So as to further increase system performance, we propose one scheme: the multiplication-after-write (MA K) method. Applying MAW method with R8-FFT unit, the resulting FFT/IFFT design not only leads to the balancing pending cycle, but also abbreviating computation latency to 8 clock cycles. Consequently, adopting the above proposed two units and one scheme, the whole chip consumes 22.36mW under 1.2V@20 MHz in TSMC 0.13 1P8M CMOS process.
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
(2008-08-01)
Lin, Chin-Teng
;
Yu, Yuan-Chu
;
Van, Lan-Da
;
資訊工程學系
;
電機學院
This investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
(2008-08-01)
Lin, Chin-Teng
;
Yu, Yuan-Chu
;
Van, Lan-Da
;
資訊工程學系
;
電機學院
This investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.
VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design
(2007-08-01)
Van, Lan-Da
;
Lin, Chin-Teng
;
Yu, Yuan-Chu
;
資訊工程學系
;
電控工程研究所
In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFF/IDFI' architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 mu W under 1.2 V@20MHz in TSMC 0.13 IP8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.