Browsing by Author "Zeng, Yuping"

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Monolithic 3D CMOS Using Layered Semiconductors
(2016-04-06)
Sachid, Angada B.
;
Tosun, Mahmut
;
Desai, Sujay B.
;
Hsu, Ching-Yi
;
Lien, Der-Hsien
Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.
Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support
(2015-05-01)
Zeng, Yuping
;
Kuo, Chien-I
;
Hsu, Chingyi
;
Najmzadeh, Mohammad
;
Sachid, Angada
A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 mu A/mu m(2) at V-GS = V-DS = 0.4 V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.
Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs
(2016-11)
Hsu, Ching-Yi
;
Zeng, Yuping
;
Chang, Chen-Yen
;
Hu, Chenming
;
Chang, Edward Yi
An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper also reveals that the nonuniformity in InAs/GaSb vertical tunneling FETs can be mitigated with the optimized band offset of heterojunction, scaling of oxide thickness, and acute angle etching profile.