Browsing by Author "Zhang, Jun-Lin"

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Improving Interface State Density and Thermal Stability of High-kappa Gate Stack Through High-Vacuum Annealing on Si0.5Ge0.5
(2019-05-01)
Lee, Wei-Li
;
Yu, Cheng-Yu
;
Zhang, Jun-Lin
;
Luo, Guang-Li
;
Chien, Chao-Hsin
We fabricated HfO2-based gate stacks on epi-Si0.5Ge0.5 substrates and investigated the effect of thermal treatment on their structural and electrical properties at varying temperatures and pressures in oxygen ambient. The thermal treatment process led to severe degradation of interface quality as the temperature increased. Material analyses indicated that annealing in oxygen ambient resulted in oxygen diffusion from the high-k material to the SiGe surface, causing undesirable SiGe reoxidation. In high-vacuum annealing, an interface state density of approximately 1.4 x 10(11) eV(-1) cm(-2) and a thermal stability of up to 500 degrees C were achieved for the gate stack on SiGe.
Study of High-Ge-Content Si0.16Ge0.84 Gate Stack by Low Pressure Oxidation
(2018-01-01)
Lee, Wei-Li
;
Zhang, Jun-Lin
;
Tsai, Ming-Li
;
Wang, Shin-Yuan
;
Luo, Guang-Li
In this study, we employed low-pressure oxidation (LPO) to achieve a high-quality dielectric gate stack on high-Ge-content (HGC) Si0.16Ge0.84. According to X-ray photoelectron spectroscopy depth-profiling results, lowering the oxidation pressure can drive out-diffusion of Si atoms from the HGC SiGe surface, resulting in the suppression of GeOx formation. A nearly GeOx-free interfacial layer detected at an O-2 pressure of 0.01 torr at 600 degrees C was used. Consequently, the formation of stable SiOx resulted in the improvement of D-it and gate leakage current, which in accumulation (V-FB-1V) was also considerably reduced with an equivalent oxide thickness of 1.5 nm. Finally, by applying the LPO process and optimized process conditions, the interface trap density (D-it) was reduced to 2 x 10(12) eV(-1) cm(-2). (C) 2018 The Electrochemical Society.