Browsing by Author "Zhao, Yan"

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A 0.55THz Y-Vector Network Configured Beam Steering Phased Array in CMOS Technology
(2018-01-01)
Zhao, Yan
;
Al Hadi, Richard
;
Lu, Hsin-Chia
;
Tseng, Tzu-Shiuan
;
Zhang, Yan
A Y-vector oscillator network is devised to configure (sub)-mm-wave/terahertz (THz) beamforming systems with minimized footprint and energy consumption. It requires no traditional adjustable phase shifter at multi-channel front end which usually suffer from high insertion loss at these frequencies. A compact (1.4mm(2)) CMOS 1x4 Beam Steering Phased Array (BSPA) based on this network is validated at 0.55THz with +/- 30 degrees steering angle range. This is the first monolithic BSPA reported beyond 0.5THz.
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
(2016-12-01)
Zhao, Yan
;
Chen, Zuow-Zun
;
Du, Yuan
;
Li, Yilei
;
Al Hadi, Richard
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
(2016-12)
Zhao, Yan
;
Chen, Zuow-Zun
;
Du, Yuan
;
Li, Yilei
;
Al Hadi, Richard
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
An Integrated 0.56THz Frequency Synthesizer with 21GHz Locking Range and-74dBc/Hz Phase Noise at 1MHz Offset in 65nm CMOS
(2016)
Zhao, Yan
;
Chen, Zuow-Zun
;
Virbila, Gabriel
;
Xu, Yinuo
;
Al Hadi, Richard