Browsing by Author "Zheng, Yan-Xiu"

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A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
(2007)
Wong, Cheng-Chi
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Tang, Cheng-Hao
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Lai, Ming-Wei
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Zheng, Yan-Xiu
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Lin, Chien-Ching
This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.
A turbo coding system for high speed communications
(2007-10-01)
Zheng, Yan-Xiu
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Su, Yu T.
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電信工程研究所
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Institute of Communications Engineering
This paper presents a new turbo coding scheme for high data rate applications. It uses a special interleaver structure that is naturally suited for parallel processing and a multiple-round early stopping test involving both sign check and a CRC code. A memory (storage) management mechanism is included as a critical part of the decoder. The proposed coding scheme offers new design options and tradeoffs that are not available to conventional convolutional turbo codes (CTCs). In particular, it becomes possible for the decoder to employ an efficient inter-block collaborative decoding algorithm, passing the information obtained from stopping test proved blocks to other unproved blocks. It also becomes important to have a proper decoding schedule. The combined effect is improved performance and reduction in the average decoding latency. We show that the memory manager has a modular-like effect in that additional memory units render enhanced performance due not only to less forced early stopping but to possible increases of the interleaving depth. It also provides additional design tradeoff amongst performance, speed and required memory size. Depending on the decoding schedule, the degree of parallelism and other decoding resources available, the proposed scheme admits a variety of decoder architectures that meet a large range of speed and performance demands.
On the Coding Scheme for Joint Channel Estimation and Error Correction over Block Fading Channels
(2009)
Wu, Chia-Lung
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Chen, Po-Ning
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Han, Yunghsiang S.
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Zheng, Yan-Xiu
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電信工程研究所
In this work, we propose a novel systematic code construction scheme for joint channel estimation and error correction for channels with independently varying fading subblocks. Unlike the existing noncoherent codes that are designed with the help of computer search, a code of desired code length and code rate can be directly generated with our coding scheme. We then compare our codes with the three-times-repetitive (12, 6) code proposed by Xu et al. for use of channel quality indicator (CQI) in uplink control for IEEE 802.16m. Simulations show that our constructed (36, 6) code has comparable performance to Xu's code when channel coefficients changes randomly in every 12 symbols. If the channel taps remain constant in the entire coding block of length 36, our code outperforms Xu's code by 0.7 dB. This indicates that the new constructed code adapts more robustly to the two simulated scenarios. For frequency selective channels of unit memory order, our simulation results suggest that our code that takes in consideration the varying characteristic of channels can achieve better performance at median-to-high signal-to-noise ratio over the computer-searched, union-bound-minimized code of length less than the varying subblock size. A side advantage of our code construction scheme is that its systematic structure makes it maximum-likelihoodly decodable by the priority-first search algorithm. The decoding complexity is therefore significantly decreased in contrast to that of exhaustive decoder for the structureless computer-searched codes.
Product codes and parallel concatenated product codes
(2007)
Huang, Tina D. -H.
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Chang, Chi-Yuan
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Zheng, Yan-Xiu
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Su, Yu T.
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電信工程研究所
We study the decoding of product codes and a class of parallel concatenated product codes (PCP/). PCPC improves the minimum distance while retaining the merit of low decoding complexity of turbo product codes (TPC). We prove that using the Fibonacci interleaver does help increasing the minimum distance. The regularity of the interleaver also reduces the implementation complexity and makes parallel interleaving feasible. We show that Pyndiah's algorithm for decoding product codes produce an annealing effect similar to that of the so-called annealed belief propagation (ABP) algorithms which adjusts the "temperature" of an augmented cost surface. Decoding methods based on modified Pyndiah and annealed BCJR algorithms for both PC and PCPC are proposed and their performance is compared.