Browsing by Author "Zhu, SY"

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Germanium pMOSFETs with Schottky-barrier germanide S/D, high-kappa gate dielectric and metal gate
(2005-02-01)
Zhu, SY
;
Li, R
;
Lee, SJ
;
Li, MF
;
Du, AY
Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as similar to5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.
High performance metal-gate/high-kappa, MOSFETs and GaAs compatible RF passive devices on Ge-on-Insulator tlechnology
(2004)
Chin, A
;
Kao, HL
;
Yu, DS
;
Liao, CC
;
Zhu, C
We propose and demonstrate a new VLSI structure using high performance metal-gate/high-kappa MOSFETs and high-Q RF passive devices on Ge-on- Insulator (GOI) platform. In additional to high RF performance passive devices on insulating Si formed by ion implantation. the metal-gate/(La)AiO(3)/GOI MOSFETs have 1.7-2.0X improved electron and hole mobility with the merits of minimizing interfacial reaction., high-kappa crystallization, Fermi-level pinning, and impurity diffusion due to low thermal budget of 500 degrees C RTA.
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode
(2004-10-01)
Zhu, SY
;
Yu, HY
;
Chen, JD
;
Whang, SJ
;
Chen, JH
Both P- and N-channel MOSFET's with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420degreesC. PMOSFETs with PtSi S/D show excellent electrical performance of an I-on/I-off similar to 10(7)-10(8) and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have similar to3 orders of magnitude larger I-off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I-on/I-off similar to 10(5) at low drain voltage. It can be attributed to the relatively higher barrier height (Phi(n)) of DySi2-x/n-Si than that of PtSi/p-Si (Phi(p)) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (similar to1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. (C) 2004 Published by Elsevier Ltd.
N-type Schottky barrier source/drain MOSFET using ytterbium silicide
(2004-08-01)
Zhu, SY
;
Chen, JD
;
Li, MF
;
Lee, SJ
;
Singh, J
Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, wich is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO2 gate dielectric, and HaN/TaN metal gate. The YbSi2-x, silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I-on/I-off ratio of similar to10(7) and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi2-x/Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.
Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode
(2004-05-01)
Zhu, SY
;
Yu, HY
;
Whang, SJ
;
Chen, JH
;
Shen, C
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.