瀏覽 的方式： 作者 Lee, Ren-Jie
顯示 1 到 10 筆資料，總共 10 筆
| 公開日期 | 標題 | 作者 |
| 1-一月-2010 | Area-I/O RDL Routing for Chip-Package Codesign Considering Regional Assignment | Lin, Kun-Sheng; Hsu, Hsin-Wu; Lee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-2013 | Board- and Chip-Aware Package Wire Planning | Lee, Ren-Jie; Hsu, Hsin-Wu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-五月-2011 | Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign | Lee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2007 | Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesign | Lee, Ren-Jie; Lai, Ming-Fang; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-2009 | Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign | Lee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2011 | On Routing Fixed Escaped Boundary Pins for High Speed Boards | Tsai, Tsung-Ying; Lee, Ren-Jie; Chin, Ching-Yu; Kuan, Chung-Yi; Chen, Hung-Ming; Kajitani, Yoji; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 21-Apr-2011 | Pin-out Designation Method for Package-Board Codesign | Lee, Ren-Jie; Chen, Hung-Ming |
| 2011 | Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow | Lee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Mar-2013 | A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow | Lee, Ren-Jie; Chen, Hung-Ming; 交大名義發表; National Chiao Tung University |
| 2009 | 晶片—封裝—印刷電路板共同設計之演算法 | 李仁傑; Lee, Ren-Jie; 陳宏明; Chen, Hung-Ming; 電子研究所 |
