Pin-out Designation Method for Package-Board Codesign

Abstract

A pin out designation method for package board codesign having steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns, use the pin patterns to construct multiple pin blocks, group the pin blocks around four sides of a chip and adjusts the pin blocks into a minimized package size of the chip.