設置晶圓上應用於晶圓接受測試之高動態範圍12位元雙斜率電流輸入類比數位轉換電路實現

Abstract

本論文提出設置晶圓上應用於Wafer acceptance test (WAT)之電流量測高動態範圍雙斜率電流輸入類比數位轉換電路。雙斜率電流輸入類比數位轉換電路結合兩種電路技巧，分別為「Current-to-voltage模式」與「Current模式」來達成高動態電流範圍的量測，在電路實現上不需過於複雜的類比、數位電路。 本測試晶片採用0.18-μm 1P6M CMOS製程實現，因電路將放置晶圓的切割道上，所以電路佈局的寬度限制在≦60μm，核心電路面積為0.581*0.057 mm2 (0.033 mm2)，符合佈局寬度上的限制。 高動態電流輸入類比數位轉換電路之有效量測範圍690uA-8nA，量測結果得到ADC在Current-to-voltage模式，工作在取樣頻率3.2 kS/s，得到ENOB為9.65-10.09 bits且電路的功耗為4.39 mW；操作在Current模式，工作在取樣頻率30-25 kS/s，得到ENOB為4.08-3.38 bits且電路的功耗為7.10-6.12 mW。

The thesis proposes dual slope current input ADC with an on-wafer wide-dynamic range applied in Wafer acceptance test (WAT) in order to measure current of device under test (DUT). The dual slope current input ADC combines two methods (voltage mode, current mode) for enhancing current of measurement capability. And the proposed architecture won’t use complicated analog and digital circuit skills. The test chip was fabricated in a 0.18-μm 1P6M CMOS process. The core area of the proposed circuit is 0.581*0.057 mm2 (0.033 mm2) and width of chip is less than 60μm can be fabricated on scribe line of wafer. The proposed ADC can measure range of current from 690uA to 8nA. Measurement results show ENOB of the proposed ADC is 9.65-10.09 bits under sampling rate of 3.2kS/s and consumes 4.39 mW in voltage mode. And then ENOB is 4.08-3.38 bits under sampling rate of 3kS/s-2.5kS/s and consumes 3.19-7.10 mW in current mode.