標題: 互補式金氧半八位元50MHz取樣頻率管線化類比至數位轉換器之設計與分析
The Design and Analysis of a CMOS 8bit 50MS/s Pipelined Analog-to-Digital Converter
作者: 夏志朋
Chih-Peng Hsia
吳錦川
Jiin-Chuan Wu
電子研究所
關鍵字: 類比至數位轉換器;轉換器;脈管式;Analog-to-Digital;ADC;Converter;Pipelined
公開日期: 2005
摘要: 本論文研究工作電壓 3.3 伏特, 8 位元,每秒 50 百萬次取樣頻率之管線化類比至數位轉換器( ADC ) ,並以台積電 0.35um 2P4M 互補式金氧半製程模擬與設計。本設計採用每級 1.5 位元與其數位錯誤修正技術來降低功率消耗與提升速度。主要元件如下:餘數放大器( residue amplifier ),比較器( dynamic comparator ) ,正反器 ( flip-flop ) ,加法器( adder ) 與時脈產生器( clock generator ) 。整個電路是以每級 1.5 位元共六級與最後一級 2 位元,再加上一個前端輸入保持電路所組成。並在輸入端使用拔靴帶電路提高取樣訊號的線性度;輸入信號為全差動正負一伏特信號。此類比至數位轉換器在操作時脈為每秒50百萬次時共消耗146mW。微分和積分非線性誤差在Matlab模擬別為±0.25LSB和±0.5LSB。
The thesis describes the design of a 3.3 V, 8-bit, 50M sample/s CMOS pipelined analog-to-digital converter (ADC) implemented by simulation with 0.35um double-poly four-metal process. The component in the ADC is the residue amplifier, the dynamic comparator, the flip-flop, the adder and the clock generator. The prototype ADC is implemented by an input sample-and-hold circuit (S/H), 6 identical 1.5-bit stages and a 2-bit final stage. Bootstrapping switch is needed to provide the linearity in the front-end S/H. The 1.5b/stage architecture with digital error correction is used in this ADC for low-power and high-speed considerations. The input signal is fully differential; the input range is ±1 V. The ADC converter dissipates 146mW at a 50MHz clock rate with 3.3 V single supply voltage. Typical differential nonlinearity (DNL) is ±0.25LSB and integral nonlinearity (INL) is ±0.5LSB by MATLAB simulation.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211679
http://hdl.handle.net/11536/67557
顯示於類別:畢業論文


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