具快速鎖頻及高階濾波器之全數位鎖相迴路

Abstract

一個穩定的時脈訊號在系統中扮演的重要的角色，隨著系統晶片內部參考時脈訊號的提升與製程的微縮，雜訊對於系統單晶片的影響也更加顯著，因此本論文提出一個具有快速鎖頻機制及高階濾波器之全數位鎖相迴路。頻率追鎖方面是透過線性內插的方式，能在5個參考頻率週期的時間內得到頻率鎖定。而相位追鎖方面可以選擇使用二階的全數位鎖相迴路架構或者濾雜訊能力較高的四階全數位鎖相迴路架構。 晶片設計利用TSMC 40nm GP 1P10M CMOS製程進行電路模擬與實現，除了數位控制振盪器及責任週期校正電路中的除二電路之外，皆使用台積電的標準元件資料庫(Standard Cell Library)，因此在製程的轉換上可縮短設計所需時間。整體電路的核心面積為0.0198mm2，鎖定時間為72個參考頻率週期。操作在輸出訊號為5GHz且輸入參考時脈訊號為96MHz的情況下，整體功率消耗為4.86mW，功率消耗和功率延遲乘積為0.972 mW/GHz。

A stable clock signal plays an important role in a system. As the speed of internal reference clock in the System-on-Chip (SOC) increased and the scaling down of the process, the effect of noise is more significant to the SOC. Therefore, a fast locking all-digital phase-locked loop (ADPLL) with higher-order filter is proposed in the thesis. At the frequency acquisition mode, the locking time is 5 cycles of the reference clock period by using the method of linear interpolation. On the other hand, at the phase tracking mode, the proposed ADPLL can select the loop filter as a first-order or a third-order with higher filtering capability. The ADPLL can attenuate the noise by using the higher-order filter. The chip has been designed and implemented in TSMC 40nm GP 1P10M CMOS process technology. In the proposed ADPLL, all logic cells except the DCO and the divided-by 2 circuit of duty-cycle correction circuit are from standard cell library, thus, it can be easily retargeted to others CMOS technology because of the cell-based nature. The total area of the ADPLL core is 0.0198mm2. The total locking time is 72 cycles of the reference clock. The total power consumption is 4.86mW at 5GHz output frequency and 96MHz reference clock. The power delay product is 0.972 mW/GHz.