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dc.contributor.authorTseng, YKen_US
dc.contributor.authorWu, CYen_US
dc.date.accessioned2014-12-08T15:27:18Z-
dc.date.available2014-12-08T15:27:18Z-
dc.date.issued1998en_US
dc.identifier.isbn0-7803-4455-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/19540-
dc.description.abstractNew true-single-phase-clocking BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. The circuit performance of the new BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits are simulated by using HSPICE in 1 mu m BiCMOS technology. Simulation results have shown that the operating frequency of the pipelined system which is constructed by the new dynamic latch logic circuits, is 204.1 MHz under 1.5 pF output loading at 2.3 V. It is 2.86 times of the operating frequency in the CMOS TSPC dynamic pipelined system.en_US
dc.language.isoen_USen_US
dc.titleA new true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logicen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6en_US
dc.citation.spageA49en_US
dc.citation.epageA52en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000075224600164-
Appears in Collections:Conferences Paper