Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hsieh, E. R. | en_US |
dc.contributor.author | Wu, P. C. | en_US |
dc.contributor.author | Chung, Steve S. | en_US |
dc.contributor.author | Tsai, C. H. | en_US |
dc.contributor.author | Huang, R. M. | en_US |
dc.contributor.author | Tsai, C. T. | en_US |
dc.date.accessioned | 2014-12-08T15:32:43Z | - |
dc.date.available | 2014-12-08T15:32:43Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.isbn | 978-1-4673-3082-4 | en_US |
dc.identifier.issn | 1524-766X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/22854 | - |
dc.description.abstract | The manipulation of RTN-trap profiling bas been experimentally demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. This is the first being reported that the positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The Understanding of the Bulk Trigate MOSFET's Reliability Through the Manipulation of RTN Traps | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000326324800023 | - |
Appears in Collections: | Conferences Paper |