運用隨機電報訊號方法分析三閘極電晶體的多層級氧化層陷阱

Abstract

隨著互補式金氧半電晶體(CMOS)的微縮，隨機電報訊號對元件產生劇烈的汲極電流波動所造成的影響是極為重要的可靠度議題之一。 隨機電報訊號的產生是由於單一載子從基板穿隧至閘極氧化層而被捕捉的物理現象。在本篇論文中，我們可以觀察此種缺陷的物理特性，且利用改良的萃取方法去準確得知缺陷的能階以及深度。 隨著超大型積體電路微縮至22奈米，漏電問題以及大幅的變異(variation)擾動問題，使得傳統的平面電晶體將不敷未來微縮用途，因此，在1999年所提出的三閘極電晶體(trigate) 結構在近幾年受到進一步的重視。然而在這樣的新型結構中依然存在著許多問題尚待解決，根據我們的觀察隨機電報訊號就是其中一項導致變異的重要來源。本文中，我們發表的一種簡單的實驗方法來萃取隨機電報訊號缺陷在互補式金氧半電晶體通道方向和氧化層中深度的分佈位置。為了研究隨機電報訊號對三閘極電晶體的影響，我們採用平面電晶體來和三閘極電晶體做比較。由實驗結果得知，在製流中產生的隨機電報雜訊缺陷在不同結構的元件中分佈特性並不相同，亦即在三閘極電晶體中缺陷分佈位置較靠近多晶矽閘極，而在平面電晶體中缺陷位置卻較為靠近基板。此外我們發現造成多層級隨機電報訊號的原因，這是由於氧化層中兩個缺陷的位置過於接近，以至於缺陷能帶的分佈互相重疊所導致。 根據上述單一元件中多層級隨機電報雜訊的研究，我們將它運用於對於靜態隨機記憶體(SRAM, Static Random Access Memory)的影響。利用隨機電報雜訊造成門檻電壓的擾動原理，我們可以成功的解釋靜態隨機儲存器在蝴蝶圖轉換的過程中發生錯誤的機制。此外，我們由蝴蝶圖中萃取出讀取靜態雜訊邊際，並比較隨機電報訊號的產生對讀取靜態雜訊邊際的影響，在此情況下此我們觀察到隨機電報訊號將會造成讀取靜態雜訊邊際擾動，擾動範圍可由2mV至23mV。在量測中我們明顯發現蝴蝶圖受到隨機電報訊號的影響而分裂，分裂開來的層級數正好相當於多層級隨機電報訊號的層級數。此一現象將是未來使用三閘極電晶體來設計SRAM時，必需謹慎考量的一項重要微縮因素。

As CMOS devices are continuously scaled, the influence of Random Telegraph Noise (RTN) in CMOS devices is one of the most important reliability issues. The RTN phenomena are resulted from the single carrier trapped and de-trapped between the channel and the trap in the gate dielectrics. In this thesis, we have observed the physical properties of single trapped carriers through a novel RTN profiling technique. This technique enables the extraction of the lateral location and vertical depth of a single trap or multiple traps in an advanced trigate nMOSFET device. As VLSI technology scaled toward 22nm node, the short channel effect and variability are intolerant in the planar architecture. So, even FINFET structure has been proposed since 1999 which received much more attention more recently. However, there are several problems which need to be solved in such a device. According to our observation, RTN is one of the most important variation sources. In this thesis we develop a simple experiment method to extract the two dimensional distribution of RTN traps. To study the influence on trigate MOSFETs, we compare trigate devices with conventional planar devices. From the profiling results, we have found that the process-induced RTN traps are generated near poly gate in trigate devices but generated near the channel of the planar devices. In addition, we have found the origins of multi-level RTN generation, which came from the cross-section of overlap traps. Based on the results of our research of RTN at the device-level, we further investigate the impact of multiple RTN on SRAM and find a newly RTN-induced failure mechanism of SRAM successfully. Besides, we extract the RSNM from butterfly curves. Comparing the RSNM (read static noise margin) of the cell with RTN and without RTN respectively, the RSNM has been degraded from 2mV to 23mV in this work because of multi-RTN. From the measurement, butterfly curves are split into multiple levels, which is corresponding to the multiple levels of RTN in a pull-down or pull-up device directly. These phenomena are first reported and will be significant for consideration in the future design of trigate SRAM.