| 標題: | 電路理論觀點設計與電路實證(I) The Design and Verification from the Electronics Theories and Experiments (I) |
| 作者: | 張隆國 國立交通大學電機與控制工程學系 |
| 公開日期: | 2003 |
| 官方說明文件#: | NSC92-2212-E009-022 |
| URI: | http://hdl.handle.net/11536/92410 https://www.grb.gov.tw/search/planDetail?id=863361&docId=164735 |
| Appears in Collections: | Research Plans |
- A Verification-Aware Design Methodology for Thread Pipelining Parallelization / Jian, Guo-An;Chien, Cheng-An;Chen, Peng-Sheng;Guo, Jiun-In
- An automorphic approach to verification pattern generation for SoC design verification using port-order fault model / Wang, CY;Tung, SW;Jou, JY
- On automatic-verification pattern generation for SoC with port-order fault model / Wang, CY;Tung, SW;Jou, JY
- 用於高階合成之派翠網路式系統階層驗證技術 / 江宗錫;Tsung-Hsi Chiang;董蘭榮;Lan-Rong Dung
- 針對晶片系統連接網路之驗證與自動合成之研究(I) / 周景揚;JOU JING-YANG
- On-line signature verification using LPC cepstrum and neural networks / Wu, QZ;Jou, IC;Lee, SY
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