Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 董蘭榮 | en_US |
| dc.contributor.author | Dung Lan-Rong | en_US |
| dc.date.accessioned | 2014-12-13T10:39:38Z | - |
| dc.date.available | 2014-12-13T10:39:38Z | - |
| dc.date.issued | 2001 | en_US |
| dc.identifier.govdoc | NSC90-2215-E009-083 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/96685 | - |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=665762&docId=126389 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.subject | 晶片設計 | zh_TW |
| dc.subject | 驗證技術 | zh_TW |
| dc.subject | 系統階層 | zh_TW |
| dc.subject | Chip design | en_US |
| dc.subject | Verification technology | en_US |
| dc.subject | System level | en_US |
| dc.title | 對以智財單元為基系統晶片設計之驗證與測試技術開發研究---子計畫I:與組織探索階段互動之系統階層驗證技術 | zh_TW |
| dc.title | System-Level Verification Interacting with Architecture Exploration | en_US |
| dc.type | Plan | en_US |
| dc.contributor.department | 交通大學電機與控制工程系 | zh_TW |
| Appears in Collections: | Research Plans | |
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