40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Abstract

This paper presents a new bit-interleaving 12T sub-threshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical V-DD to 350 mV (similar to 100 mV lower than the threshold voltage) with V-DDMIN limited by Read operation. Data can be written successfully for V-DD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 mu W at 350 mV, 25 degrees C.