Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Abstract

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 mu m lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; similar to 124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 +/- 13 mV/V), and a high I-ON/I-OFF current ratio (similar to 1 x 10(9)) under a relatively low voltage condition (V-D = 0.3 V, V-G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area. (C) 2015 The Japan Society of Applied Physics