A well-structured modified Booth multiplier design

dc.citation.epage	88	en_US
dc.citation.spage	85	en_US
dc.contributor.author	Wang, Li-Rong	en_US
dc.contributor.author	Jou, Shyh-Jye	en_US
dc.contributor.author	Lee, Chung-Len	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:04:53Z
dc.date.available	2014-12-08T15:04:53Z
dc.date.issued	2008	en_US
dc.description.abstract	This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row-removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.	en_US
dc.identifier.isbn	978-1-4244-1616-5	en_US
dc.identifier.journal	2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/3397
dc.identifier.wosnumber	WOS:000256565800020
dc.language.iso	en_US	en_US
dc.title	A well-structured modified Booth multiplier design	en_US
dc.type	Proceedings Paper	en_US

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