A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression

dc.citation.woscount	0	en_US
dc.contributor.author	Su, Ming-Chiuan	en_US
dc.contributor.author	Chen, Wei-Zen	en_US
dc.contributor.author	Wu, Pei-Si	en_US
dc.contributor.author	Chen, Yu-Hsian	en_US
dc.contributor.author	Lee, Chao-Cheng	en_US
dc.contributor.author	Jou, Shyh-Jye	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2015-07-21T08:31:06Z
dc.date.available	2015-07-21T08:31:06Z
dc.date.issued	2013-01-01	en_US
dc.description.abstract	A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1: 5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI(pp) input data jitter, the recovered clock jitter at 2GHz is 2.94ps(rms). The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200x150 mu m(2).	en_US
dc.identifier.isbn	978-1-4673-6146-0	en_US
dc.identifier.issn		en_US
dc.identifier.journal	2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/125072
dc.identifier.wosnumber	WOS:000350887800068	en_US
dc.language.iso	en_US	en_US
dc.title	A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression	en_US
dc.type	Proceedings Paper	en_US

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