The Variability Issues in Small Scale Trigate CMOS Devices: Random Dopant and Trap Induced Fluctuations

Abstract

In this paper, the variability issues of small scale trigate CMOS devices will be presented. Two major sources of the variability are discussed, RDF (Random Dopant Fluctuation) and RTF (Random Trap Fluctuation). The former is induced by the process, while the later is induced by the devices after the electrical stress. For process-induced Vth variation, the major source of variability for conventional CMOS devices comes from the random dopant fluctuation (RDF) in the device channel. The theoretical basis from an experimental discrete dopant profiling technique will first been introduced to analyze the RDF effect. Then, for stress-induced Vth variation, the RTF will be introduced. In general, the trigate device structure has been able to suppress the RDF effect. However, the increasing RTF effect becomes critical to the development of trigate CMOS devices. More in-depth understanding of the variation for device after the electrical stress will be elucidated in this paper. The important sidewall roughness effect in the trigate device will also be addressed. Moreover, more recent results to demonstrate the stress-induced traps and the correlation to device reliability will be demonstrated.