Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack

Abstract

We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V-t) of 0.31 V. This small EOT MOSFET was achieved by employing high-kappa CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-kappa SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node. (C) 2013 Elsevier Ltd. All rights reserved.