Low power parallel Huffman decoding

Abstract

A low power design technique for a parallel Huffman decoder is presented. According to the length of the incoming Huffman codeword, the proposed strategy makes the barrel shifter in the parallel Huffman decoder turn off the unnecessary shifting bits to reduce power dissipation. The result of a SPICE simulation indicates that up to 50 percent power reduction in the barrel shifter may be achieved with the proposed technique.