Portable simulation/emulation stimulus on an industrial-strength SoC

Abstract

Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture (TM) Technology-based SoC demonstrate about a 100x speedup on the emulator vis-a-vis the simulator.