The Annealing and the Hysterisis Effects of Au+ Implanted MOS Structures

Abstract

Firstly, this work provides a convenient method, with C-V, I-V and lifetime measurements as the analytic tools, to study the annealing and hysterisis effects in Au+ implanted SiO2 MOS structures. With 70 keV Au+ implanted into 560Å thick SiO2 layer, the optimum annealing condition is at 400℃, 15 to 30 minutes in dry nitrogen gas. With stress voltages range from +24 to -30 volts applied for 1 second, the flatband voltage shift is 14 volts which corresponds to an accumulated or stored charge of -8*10^12e cm^-2 in the oxide layer. Thus the resulting MOS structure behaves similarly to a floating gate or multilayer device with obvious simplifications in the processing.