Multithreaded coprocessor interface for multi-core multimedia SoC

dc.citation.epage	22	en_US
dc.citation.spage	21	en_US
dc.contributor.author	Ou, Shih-Hao	en_US
dc.contributor.author	Lin, Tay-Jyi	en_US
dc.contributor.author	Deng, Xiang Sheng	en_US
dc.contributor.author	Zhuo, Zhi Hong	en_US
dc.contributor.author	Liu, Chih Wei	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:03:22Z
dc.date.available	2014-12-08T15:03:22Z
dc.date.issued	2008	en_US
dc.description.abstract	Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management Is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.	en_US
dc.identifier.isbn	978-1-4244-1921-0	en_US
dc.identifier.journal	2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/1919
dc.identifier.wosnumber	WOS:000257065100009
dc.language.iso	en_US	en_US
dc.title	Multithreaded coprocessor interface for multi-core multimedia SoC	en_US
dc.type	Proceedings Paper	en_US

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