A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware Keeper

Abstract

We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (V-MIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read V-MIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve V-MIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read V-MIN by 9% to 21% at low supply voltages.