Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications

Abstract

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) similar to 68 mV/dec., steep average subthreshold swing (A.S.S.) similar to 73 mV/dec., smaller drain induced barrier lowing (DIBL) similar to 9 mV/V, and higher I-on/I-off ratio similar to 1.1 x 10(8) (V-D = 1 V).