Performance constraints aware voltage islands generation in SoC floorplan design

Abstract

Using voltage island methodology to reduce power consumption for System-on-a-Chip SoQ designs has ecome more and more popular rec. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IEP) are widely used, it is necessary to optimize floorplanning/placement methodolo considering voltage islands generation to solve power anFcritical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in mosules.